Cirrus Logic CS4953xx, Hardware User Manual

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Typical Connection Diagrams
CS4953xx Hardware Users Manual
DS732UM7 Copyright 2008 Cirrus Logic, Inc 9-1
Chapter 9
System Integration
9.1 Typical Connection Diagrams
Figure 9-1 is a typical connection diagram (LQFP-144) showing I
2
C control with a serial FLASH, SDRAM and up
to 7 DACs. Serial FLASH is recommended over parallel flash because it makes SDRAM layout much easier. This
configuration uses the default settings for serial FLASH chip select (pin 6).
Figure 9-2 is a typical connection diagram (LQFP-144) showing SPI control with a serial FLASH, SDRAM and up
to 7 DACs. This configuration uses the default settings for serial FLASH chip select (pin 6).
Figure 9-3 is a typical connection diagram (LQFP-144) showing SPI control with a serial FLASH, SDRAM and up
to 8 DACs. This configuration allows the system to connect the maximum number of DACs to the DSP by using an
alternate chip select for the serial FLASH (pin 121).
Figure 9-4 is a typical connection diagram (LQFP-144) showing I
2
C control with parallel FLASH, SDRAM and up
to 8 DACs. This configuration is not preferred because the SDRAM and FLASH share a bus, making routing more
difficult.
Figure 9-5 is a typical connection diagram (LQFP-128) showing SPI control with parallel FLASH, SDRAM and up
to 8 DACs. This configuration is not preferred because the SDRAM and FLASH share a bus, making routing more
difficult.
Figure 9-6 is a typical connection diagram (LQFP-128) showing I
2
C control with parallel FLASH, SDRAM and up
to 8 DACs. This configuration is not preferred because the SDRAM and FLASH share a bus, making routing more
difficult.
Figure 9-7 is a typical connection diagram (LQFP-144) showing SPI control with a serial FLASH, SDRAM and up
to 7 DACs. This configuration uses the default settings for serial FLASH chip select (pin 6).
Figure 9-8 is a typical connection diagram (LQFP-144) showing SPI control with a serial FLASH, DSD Audio
Input, SDRAM and up to 7 DACs.
Place PLL filter components as close as possible to the DSP. A unified, solid ground plane is recommended for
optimal performance. Pay close attention to the direction of all clock signals shown in the diagram. These designs
are configured to slave to clocks on the input side. On the output side, the DSP slaves to MCLK from the S/PDIF
receiver and masters SCLK and LRCLK for the DACs. This is the recommended clocking for AVR applications.
Series Termination resistor values depend on the transmission line impedances of the actual PCB used. The design
engineer should calculate the transmission line impedance of the traces and size the series R such that R = (Z – 15),
where 15 represents the source impedance of the CS4953xx drivers.
The typical connection diagrams show “0.1uF x 8” to indicate that 1 decoupling capacitor should be placed next to
each power pin.
The SDCLK termination used in the typical connection diagrams, and on the CRD49530, is an AC parallel
terminator. The proper board layout for this kind of termination is to route the SDRAM Clock signal to the
SD_CLKIN pin and then beyond the pin a short distance before connecting to the parallel termination. The resistor
and capacitor should be the last components on that trace (terminating the trace).