Cirrus Logic CS4953xx, Hardware User Manual

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3-9 Copyright 2008 Cirrus Logic, Inc. DS732UM7
I2C Port
CS4953xx Hardware Users Manual
3.2.3.3 I
2
C Write Protocol
1. An I
2
C transfer is initiated with an I
2
C start condition which is defined as the data (SCP1_SDA) line falling
while the clock (SCP1_CLK) is held high.
2. This is followed by a 7-bit address and the read/write bit held low for a write. So, the master should send 0x80.
The 0x80 byte represents the 7-bit I
2
C address 1000000b, and the least significant bit set to ‘0’, designates a
write.
3. After each byte (including the address and each data byte) the master must release the data line and provide a
ninth clock for the CS4953xx DSP (slave) to acknowledge (ACK) receipt of the byte. The CS4953xx will drive
the data line low during the ninth clock to acknowledge. If for some reason CS4953xx does not acknowledge
(NACK), it means that the communications channel has been corrupted and the CS4953xx should be re-booted.
A NACK should never happen here.
4. The master should then clock one data byte into the device, most-significant bit first.
5. The CS4953xx (slave) will (and must) acknowledge (ACK) each byte that it receives which means that after
each byte, the master must provide an acknowledge clock pulse on SCP1_CLK and release the data line,
SCP1_SDA.
6. If the master has no more data words to write to the CS4953xx, then proceed to Step 8. If the master has more
data words to write to the CS4953xx, then proceed to Step 7.
7. The master should poll the SCP1_BSY signal until it goes high. If the SCP1_BSY signal is low, it indicates that
the CS4953xx is busy performing some task that requires pausing the serial control port. Once the CS4953xx is
able to receive more data words, the SCP1_BSY signal will go high. Once the SCP1_BSY signal is high,
proceed to Step 4. Note: The DSP’s I
2
C port also implements clock stretching to indicate that the host should
pause communication. So the host has the option of checking for SCP1_CLK held low rather than SCP1_BSY
low.
8. At the end of a data transfer, a stop condition must be sent. The stop condition is defined as the rising edge of
SCP1_SDA while SCP1_CLK is high.
3.2.3.4 Performing a Serial I
2
C Read
Information provided in this section is intended as a functional description indicating how to use the configured
serial control port to perform an I
2
C read from an external device (master) to the CS4953xx DSP (slave). The system
designer must ensure that all timing constraints of the I
2
C Read Cycle are met (see the CS4953xx datasheet for
timing specifications). I
2
C read transactions from the CS4953xx will always involve reading 4-byte words.
Figure 3-9 illustrates the sequence of events that define the I
2
C read protocol for SCP1. This protocol is discussed in
the high-level procedure found in Section 3.2.3.5.