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9-29

DS732UM7

Revision History
CS4953xx Hardware Users Manual

9.8 Revision History

§§

Revision

Date

Changes

UM1

MAY 17, 2006

Preliminary Release

UM2

AUG 24, 2006

Updated Boot Procedure

UM3

OCT 11, 2007

Updated CrusConfig register and corrected Output D1
and Input D2 messages. Update

Section 2.4.2,

"Softboot Procedure" on page 2-15

UM4

NOV 21, 2007

Added Bank Addressing note to

Table 8-1

for SD_BA0/

EXT_A13 and SD_BA1/EXT_A14 signals. Added same
note with each schematic in Chapter 9. Modified Note
directly above

Section 8.3.1, "SDRAM/Flash Interface

Signals" on page 8-2

UM5

NOV 28, 2007

Changed definition for secondary functions in

Section 9-

10 “Pin Assignments” on page 9-17

for pins 138 and

142. Made same changes in

Figure 9-11

for the 144-Pin

LQFP pin layout drawing.

UM6

May 7, 2008

Changed text in Figure Titles for

. Modified Note 1 under

Table

8-1

. Change note regarding bank selection, in Figures

9-1 to 9-7. Added new typical connection diagram in

Figure 9-6

, “LQFP-128, I

C Control, Serial FLASH, DSD

Audio Input, SDRAM, 7 DACs.” Modified description of
firmware modules offered on the CS4953xx platform on
page 1-3. Updated list of sample rates supported for the
Digital Audio Port in

Section 6.1, "Description of Digital

Audio Input Port when Configured for DSD Input" on
page 6-1

. Clarified availability of parallel control port in

Chapter 4, "Parallel Control Port"

UM7

July 10, 2008

Added important notice a beginning of

Section 8.3.2,

"Configuring SDRAM/Flash Parameters" on page 8-4

Summary of Contents for CS4953xx

Page 1: ...732UM7 http www cirrus com CS4953x 32 bit Audio DSP Family Preliminary Product Information This document contains information for a new product Cirrus Logic reserves the right to modify this product without notice CS4953xx Hardware Users Manual ...

Page 2: ...round are trademarks of Cirrus Logic Inc All other brand and product names in this document may be trademarks or service marks of their respective owners Dolby Dolby Digital Dolby Headphone Dolby Virtual Speaker AC 3 and Pro Logic are registered trademarks of Dolby Laboratories Inc AAC Dolby Headphone2 Dolby Virtual Speaker2 and Dolby Digital Surround EX are trademarks of Dolby Laboratories Inc Su...

Page 3: ...rs 1 6 1 2 15 Clock Manager and PLL 1 6 1 2 16 Programmable Interrupt Controller 1 7 Chapter 2 Operational Modes 2 1 2 1 Operational Mode Selection 2 3 2 2 Slave Boot Procedures 2 3 2 2 1 Host Controlled Master Boot 2 4 2 2 1 1 Performing a Host Controlled Master Boot HCMB 2 5 2 2 2 Slave Boot 2 7 2 2 2 1 Performing a Slave Boot 2 8 2 2 3 Boot Messages 2 10 2 2 3 1 Slave Boot 2 10 2 2 3 2 Host Con...

Page 4: ...nput Port Description 5 1 5 1 1 DAI Pin Description 5 1 5 1 2 Supported DAI Functional Blocks 5 2 5 1 3 BDI Port 5 2 5 1 4 Digital Audio Formats 5 4 5 1 4 1 I2 S Format 5 4 5 1 4 2 Left Justified Format 5 4 5 2 DAI Hardware Configuration 5 4 5 2 1 DAI Hardware Naming Convention 5 5 Chapter 6 Direct Stream Data DSD Input Interface 6 1 6 1 Description of Digital Audio Input Port when Configured for ...

Page 5: ...ignments 9 17 9 8 Revision History 9 21 Figures Figure 1 1 CS4953xx Chip Functional Block Diagram 1 2 Figure 2 1 Operation Mode Block Diagrams 2 2 Figure 2 2 Host Controlled Master Boot 2 5 Figure 2 3 Slave Boot Sequence 2 8 Figure 2 4 Master Boot Sequence Flowchart 2 13 Figure 2 5 Soft Boot Sequence Flowchart 2 15 Figure 2 6 Soft Boot Example Flowchart 2 16 Figure 3 1 Serial Control Port Internal...

Page 6: ... Formats Rising Edge Valid 7 3 Figure 7 3 Left justified Digital Audio Formats Rising Edge Valid DAO_SCLK 7 3 Figure 7 4 One line Data Mode Digital Audio Formats 7 4 Figure 8 1 SDRAM Interface Block Diagram 8 1 Figure 9 1 LQFP 144 I2 C Control Serial FLASH SDRAM 7 DACs 9 2 Figure 9 2 LQFP 144 SPI Control Serial FLASH SDRAM 7 DACs 9 3 Figure 9 3 LQFP 144 SPI Control Serial FLASH SDRAM 8 DACs 9 4 Fi...

Page 7: ...C 5 7 Table 5 6 Input DAI Mode Configuration Input Parameter D 5 8 Table 6 1 DSDl Audio Input Port 6 1 Table 7 1 Digital Audio Output DAO1 DAO2 Pins 7 1 Table 7 2 Output Clock Mode Configuration Parameter A 7 5 Table 7 3 DAO1 DAO2 Clocking Relationship Configuration Parameter B 7 5 Table 7 4 Output DAO_SCLK LRCLK Configuration Parameter C 7 5 Table 7 5 Output Data Format Configuration Parameter D ...

Page 9: ...n consumer entertainment products In addition external SDRAM and Flash memory interfaces can be used to expand the data memory This device is suitable for a variety of high performance audio applications These include Audio Video Receivers DVD Receivers Stereo TVs Mini Systems Shelf Systems Digital Speakers Car Audio Head Units and Amplifiers Set top Boxes 1 1 1 Chip Features The CS4953xx includes...

Page 10: ...mulators X Y P X P Y 64 bit Stereo Audio Output Stereo Audio Output Stereo Audio Output Arbiter Arbiter Stereo Audio Output or SPDIF Transmitter DAO Controller ROM SRAM ROM SRAM ROM SRAM Timers GPIOs Clock Manager and PLL Parallel Control Port Serial Control Port SDRAM Controller SRAM FLASH Controller Debug Controller DSPA DSPB DAO1 Stereo Audio Input DSD Stereo Audio Input DSD Stereo Audio Input ...

Page 11: ...r Cirrus Framework modules and the associated application notes are available through the Cirrus Software Licensing Program Standard post processing code modules are only available to customers who qualify for the Cirrus Framework CS4953xx Family DSP Programming Kit Please refer to the Related Documents section of the Framework manual for additional application note information The CS4953xx contai...

Page 12: ...e allows the DBC to insert instructions into the pipeline The core will acknowledge the action when it determines the pipeline is in the appropriate state for the inserted action to be taken 1 2 4 Digital Audio Output DAO1 DAO2 Controller The CS4953xx has two Digital Audio Output DAO controllers each of which contains 4 stereo output ports One port on each DAO can be used as a S PDIF transmitter T...

Page 13: ...de selection occurs as the CS4953xx exits a reset condition The rising edge of the RESET pin samples the HS 4 0 pins to determine the communication mode and boot style Configuration of the three address input pins A 2 0 allows one of the parallel configuration registers to be selected and accessed 1 2 10 Serial Control Ports SPI or I2C Standards The CS4953xx has two serial control ports SCP that s...

Page 14: ...or the S PDIF transmitters 4 for the DAI and one for the parallel control port The addition of the DMA channel for the parallel control port allows compressed audio data to be input over this port The DMA block is able to move data to from X or Y memory or alternate between both X and Y memory The DMA controller moves data to from X and or Y memory opportunistically if the core is not currently ac...

Page 15: ...priority Each interrupt has a corresponding interrupt address that is also supplied to the DSP core The interrupt address is the same as the IRQ number interrupt 0 uses interrupt address 0 and interrupt 15 uses interrupt address 15 Both an enable mask and a run mask are provided for each interrupt The enable mask allows the enabled interrupts to generate a PIC_REQ signal to the DSP core and the ru...

Page 17: ... system host controller the master boot device to determine how to boot the application code The system host controller can either load the application code or the host can direct the CS4953xx to boot application code from serial or parallel external ROM See Figure 2 1 on page 2 2 Thus there are three boot modes for the CS4953xx Master Boot From serial or parallel external ROM Slave Boot Using SPI...

Page 18: ...t Controller Master CS4953xx Slave Control Bus C S4953xx M aster E xternal R O M S lave External M em ory Bus M aster B oot N ot currently supported by O S C S4953xx Slave External R O M Ext Serial Flash Parallel M em ory Bus SC P2 System H ost C ontroller M aster C ontrol Bus Host Controlled M aster Boot R ecom m ended for m ost system s ...

Page 19: ... active low 0 cycle delay from CS Address Change to Output Enable 4 cycle delay from CS to Read Access 7 Master Boot Modes are currently not supported by the O S 8 Fdclk is specified in the CS4953xx data sheet 2 2 Slave Boot Procedures When the CS4953xx is the slave boot device the system host controller as the master boot device must follow an outlined procedure for correctly loading application ...

Page 20: ...d to the CS4953xx a KICK START message is sent to cause the application code begin execution Please note that it takes time to lock the PLL and initialize the SDRAM interface when initially booting the DSP Typically this time is less than 200 ms If a message is sent to the DSP during this time the SCP1_BSY pin will go low to indicate that the DSP is busy Any messages sent when the SCP1_BSY pin is ...

Page 21: ...G APP_START WRITE_ SOFT_RESET READ_ MSG EXIT ERROR N Y MORE ULD FILES Y N DONE SEND HARDWARE CONFIGURATIONS SEND FIRMWARE CONFIGURATIONS WRITE_ KICKSTART is replaced with SPI I2C etc depending on the communication protocol used RESET HIGH WAIT 50 μS START RESET LOW SET HS 3 0 PINS FOR OPERATIONAL MODE WAIT 10 μS WRITE_ SLAVE_BOOT MSG BOOT_START EXIT ERROR N Y WAIT 10 μS READ_ MSG NOTE 1 EXIT ERROR...

Page 22: ... image integrity should be checked if this occurs 8 Send the SOFT_RESET_DSP_A command After reading the BOOT_SUCCESS message on the boot assist code image overlay the host must send this message 9 Send the correct HCMB_ MODE message The host sends to the CS4953xx the appropriate HCMB_ MODE message where MODE indicates the type of external ROM PARALLEL SPI or I2C This message tells CS4953xx the sta...

Page 23: ...dware and software Hardware configuration messages are used to define the behavior of the CS4953xx s audio ports 19 Send Software Configuration messages The software configuration messages are specific to each application The application code User s Guide for each application provides a list of all pertinent configuration messages 20 Send the KICKSTART message The CS4953xx application locks the PL...

Page 24: ...RESET_DSP_A READ_ MSG NOTE 1 WRITE_ BOOT_ASSIST_A ULD FILE RESET HIGH WAIT 50 μS START RESET LOW SET HS 3 0 PINS FOR OPERATIONAL MODE NOTE 1 Read four bytes from the DSP IRQ will not drop for this read sequence NOTE 2 Obey IRQ for all reads from this point forward MSG BOOT_START WRITE_ SLAVE_BOOT READ_ MSG NOTE 2 EXIT ERROR N Y MSG BOOT_SUCCESS EXIT ERROR N Y READ_ MSG WRITE_ ULD FILE MSG APP_STAR...

Page 25: ...he communications interface hardware and code image integrity should be checked if this occurs 8 Send the SOFT_RESET_DSP_A command After reading the BOOT_SUCCESS message on the boot assist code image overlay the host must send this message 9 Send the SLAVE_BOOT message The host sends the appropriate SLAVE_BOOT message to the CS4953xx using the control port specified serial port parallel port and f...

Page 26: ...ll pertinent configuration messages 21 Send the KICKSTART message s The CS4953xx application locks the PLL and begins processing audio after receiving this message 2 2 3 Boot Messages The Slave Boot and Host Controlled Master Boot procedures use a number of messages to configure and synchronize the boot process Please use the messages listed below when implementing the boot process as a part of th...

Page 27: ...e A variable The I2 C clock is derived from the internal core clock This clock can be divided down with the c 12 bit divider variable The command byte the first byte to the I2C ROM can be defined by the s variable The CS4953xx control port used for the HCMB_I2C can be configured by the p variable 2 2 3 4 Host Controlled Master Boot from SPI ROM Table 2 4 HCMB_I2C message for CS4953xx MNEMONIC VALU...

Page 28: ...the S variable configures the chip select used according to Table 2 6 below 2 2 3 5 Soft Reset The SOFT_RESET message is the message sent to the CS4953xx after all of the overlays have been successfully booted The SOFT_RESET leaves execution of the bootloader and begins execution of the loaded overlays The overlays can be configured once the SOFT_RESET message has been sent 2 2 3 6 Messages Read f...

Page 29: ...ll load a single overlay from address 0x0 It should be noted that the loaded overlay must reconfigure one of the control ports to be slave to the bus for a system host controller to configure the part Thus this type of boot process will be useful in systems without a system host controller or with a simple controller that only performs a monitoring task Currently this mode is not used for any appl...

Page 30: ...e boot methods outlined in this chapter This includes a soft reset of the CS4953xx which then requires that the host send or re send the hardware and software configuration messages 2 4 1 Softboot Messaging Two messages are relevant to the softboot procedure for the CS4953xx These messages are SOFTBOOT and SOFTBOOT_ACK The SOFTBOOT message is sent from the host controller to the CS4953xx to indica...

Page 31: ... IRQ pin is LOW proceed to Step 3 3 Read the SOFTBOOT_ACK message If the message is the SOFTBOOT_ACK message 0x00000005 then the host should proceed to Step 4 If the message is not the SOFTBOOT_ACK message the host should return to Step 2 4 Load Overlays Repeat the boot procedure used to originally load the overlays into the CS4953xx for example SLAVE_BOOT HCMB_ MODE but only the overlays that nee...

Page 32: ...t is most commonly used CS4593x systems Figure 2 6 Soft Boot Example Flowchart MSG BOOT_START WRITE_ HCMB_ MODE READ_ MSG N Y MSG BOOT_SUCCESS N Y READ_ MSG MSG APP_START WRITE_ SOFT_RESET READ_ MSG N Y MORE ULD FILES Y N DONE SEND HARDWARE CONFIGURATIONS SEND FIRMWARE CONFIGURATIONS WRITE_ KICKSTART is replaced with SPI I2C etc depending on the communication protocol used EXIT ERROR EXIT ERROR EX...

Page 33: ... correct after the download If the checksum was incorrect CS4953xx responds with a BOOT_ERROR_CHECKSUM message This indicates that the image read by the DSP is corrupted The communications interface hardware and code image integrity should be checked if this occurs 9 Repeat Steps 4 8 for all code images Overlays The host repeats these steps until all overlays for the application have been successf...

Page 35: ...nt The main difference between the two is the actual protocol being implemented between the CS4953xx and the host In addition the I2 C slave has a true I2 C mode that utilizes data flow mechanisms inherent to the I2 C protocol If this mode is enabled the I2 C slave will hold SCP1_CLK low to delay a transfer as needed this is in addition to activating SCP1_BSY The CS4953xx has two serial ports Howe...

Page 36: ...ave The CS4953xx has two serial ports However the O S currently supports only slave mode host communication on SCP1 and master mode communication on SCP2 for booting from a serial EEPROM FLASH The I2C bus is a multi master bus This means that more than one device capable of controlling the bus can be connected to it The master slave relationships found on the I2 C bus are not permanent and only de...

Page 37: ...tput in SPI mode In serial slave mode this pin serves as the serial control clock input In I2 C slave mode the clock can be pulled low by the port to stall the master 99 126 Open Drain SCP1_SDA Bidirectional Data I2C Mode Master Slave Data IO In I2C master and slave mode this open drain pin serves as the data input and output 97 124 Open Drain SCP1_IRQ Control Port Data Ready Interrupt Request Out...

Page 38: ...tions are functionally identical Figure 3 3 I2 C Start and Stop Conditions SCP2_CLK I2 C Control Port Bit Clock In master mode this pin serves as the serial control clock output open drain in I2C mode output in SPI mode In serial slave mode this pin serves as the serial control clock input In I2 C slave mode the clock can be pulled low by the port to stall the master 103 1 Open Drain SCP2_SDA Bidi...

Page 39: ...CK and NACK For write operations the R W bit must be set to zero R W 0 Address 0x80 After the 8 bit data byte has been clocked the master will release the SCP1_SDA line If the slave received the byte correctly it will drive the SCP1_SDA line low for the next bit clock to acknowledge ACK that the data was received If the data was not received correctly the slave can communicate this by leaving the ...

Page 40: ...ew transfer or a Stop condition as shown in Figure 3 7 to abort the transfer Figure 3 6 Repeated Start Condition with ACK and NACK Start SCP1_CLK SCP1_SDA A 6 A 5 A 4 A 3 A 2 A 1 A 0 R W ACK Data Byte ACK M S M S Write M S S M Read Start SCP1_CLK SCP1_SDA A 6 A 5 A 4 A 3 A 2 A 1 A 0 R W ACK Data Byte NACK M S M S Write M S S M Read M Master Drives SDA S Slave Drives SDA SCP1_CLK SCP1_SDA Data Byte...

Page 41: ...e words used for control and application image download A detailed description of the serial SPI communication mode is provided in this section This includes A flow diagram and description for a serial I2 C write A flow diagram and description for a serial I2 C read 3 2 3 1 SCP1_BSY Behavior The SCP1_BSY signal is not part of the I2 C protocol but it is provided so that the slave can signal to the...

Page 42: ...d in this section will be used when writing single word messages to the boot firmware writing multiple word overlay images to the boot firmware and writing multiple word messages to application firmware The examples given can therefor be expanded to fit any I2C writing situation The flow diagram shown in Figure 3 8 illustrates the sequence of events that define the I2 C write protocol for SCP1 Sec...

Page 43: ...data words to write to the CS4953xx then proceed to Step 8 If the master has more data words to write to the CS4953xx then proceed to Step 7 7 The master should poll the SCP1_BSY signal until it goes high If the SCP1_BSY signal is low it indicates that the CS4953xx is busy performing some task that requires pausing the serial control port Once the CS4953xx is able to receive more data words the SC...

Page 44: ...igure 3 9 I2 C Read Flow Diagram SCP1_IRQ LOW BYTES READ 4 Y N N Y SEND I2C STOP DRIVE SCP1_SDA HIGH WHILE SCP1_CLK IS HIGH SCP1_IRQ LOW Y N START SEND I2C START DRIVE SCP1_SDA LOW WHILE SCP1_CLK IS HIGH WRITE ADDRESS BYTE 0x81 READ DATA BYTE SEND ACK SEND NACK SCP1_SDA ACK Y N EXIT ERROR ...

Page 45: ...ACK should never happen here 5 The data is ready to be clocked out on the SCP1_SDA line at this point Data clocked out by the host is valid on the rising edge of SCP1_CLK and data transitions occur just after the falling edge of SCP1_CLK 6 After the CS4953xx has written the byte to the master on the SCP1_SDA line it will release the SCP1_SDA line If the master has more bytes in the 4 byte word to ...

Page 46: ...or the last bit of the last byte read from the I2 C slave 4 A NACK is sent by the master after the last byte to indicate the end of the read cycle This must be followed with an I2C Stop condition or I2C Repeated Start condition 5 If there are more data words to read IRQ will fall at the rising edge of CLK for the NACK Otherwise IRQ remains high until an I2 C Stop condition or an I2C Repeated Start...

Page 47: ...ould send an I2C stop condition to complete the read sequence If SCP1_IRQ is still low after the rising edge of SCP1_CLK on the last data bit of the current byte the master should send an acknowledge and continue reading data from the serial control port It should be noted that all data should be read out of the serial control port during one cycle or a loss of data will occur In other words all d...

Page 48: ...o further messages This pin reflects the state of the SCP1 port Transmit Buffer Empty Flag 100 4 Open Drain SCP1_BSY Serial Control Port 1 Input Busy Output Active Low This pin is driven low when the control port s receive buffer is full This pin reflects the state of the SCP1 or PCP Receive Buffer Full Fag 102 128 Open Drain SCP2_CS SPI Chip Select Active Low In serial SPI slave mode this pin is ...

Page 49: ... systems that are booting from serial EEPROM 3 3 2 SPI Bus Dynamics A SPI transaction begins by the master driving the slave chip select SCP1_CS low SPI transactions end by the master driving the SCP1_CS high This SPI bus is considered busy while any device s SCP1_CS signal is low The bus is free only when all slave SCP1_CS signals are high A high to low transition on the SCP1_CS line defines an S...

Page 50: ... that it cannot receive any more data A falling edge of the SCP1_BSY signal indicates the master must halt transmission Once the SCP1_BSY signal goes high the suspended transaction may continue The host must obey the SCP1_BSY pin or control data will be lost 3 3 3 SPI Messaging Messaging to the CS4953xx using the SPI bus requires usage of all the information provided in the SPI Bus Description and...

Page 51: ... the chip select SCP1_CS is driven low SCP1_CS driven low indicates that CS4953xx is in SPI slave mode 2 This is followed by a 7 bit address and the read write bit set low for a write So the master should send 0x80 The 0x80 byte represents the 7 bit SPI address 1000000b and the least significant bit set to 0 designates a write 3 The master should then clock the 4 byte data word into the slave devi...

Page 52: ...he SPI read cycle are met see the CS4953xx datasheet for timing specifications When performing a SPI read the same protocol is used whether reading a single byte or multiple bytes From a hardware perspective it makes no difference whether communication is a single byte or multiple bytes of any message length so long as the correct hardware protocol is followed The example shown in this section can...

Page 53: ... significant bit set to 1 designates a read 4 After the falling edge of the serial control clock SCP1_CLK for the read write bit the master can begin clocking out the 4 byte word from the CS4953xx on the MISO pin Data clocked out of the CS4953xx by the master is valid on the rising edge of SCP1_CLK and data transitions occur on the falling edge of SCP1_CLK The serial clock should be held low so th...

Page 54: ... rising edge of the clock for the last bit of the last byte to be read from the SPI slave 2 After going high IRQ remains high until the CS signal is raised to end the SPI transaction If there are more bytes to read IRQ will fall after CS has gone high SCP1_CLK SCP1_MOSI Data Byte 3 MSB 7 bit Address R W Data Byte 2 D SCP1_CS SCP1_CLK SCP1_MOSI Data Byte 3 MSB 7 bit Address R W Data Byte 2 Data Byt...

Page 55: ...t of CS4953xx If there is no more data to be transferred SCP1_IRQ will go high at this point After going high SCP1_IRQ is guaranteed to stay high until the rising edge of SCP1_CS This end of transfer condition signals the master to end the read transaction by clocking the last data bit out of CS4953xx and then driving the CS4953xx SCP1_CS line high to signal that the read sequence is over If SCP1_...

Page 57: ... sales representative if you need to use this port The CS4953xx is equipped with an 8 bit Parallel Control Port that can be used for host communication providing faster control throughput for the system The Parallel Control Port is capable of Intel Motorola and Multiplexed Intel communication modes Note The Parallel Control Port is not available on S4953xx products using the 128 Pin LQFP package ...

Page 59: ...igured to load audio samples in a number of formats or accept multiple stereo channels on a single input port DAI features include Five digital audio input pins capable of supporting many audio formats Two independent input clock domains DAI1_SCLK DAI1_LRCLK or DAI2_SCLK DAI2_LRCLK Up to 32 bit data widths Sample rates up to 192 kHz Two simultaneous serial compressed audio data inputs in IEC61937 ...

Page 60: ...e Currently not supported in the O S The Bursty Data Input BDI port on the CS4953xx shares pins with the DAI port pins and is used for input of bursty compressed audio data The compressed data is clocked in with a bit clock BDI_CLK Bursty compressed DAI1_DATA0 PCM or Compressed Audio Input Data 0 PCM Audio Input Data 0 Serial data input that can accept PCM audio data that is synchronous to DAI_SCL...

Page 61: ...ery flow control output for bursty audio data It indicates whether the DSP can accept more data 140 32 Output BDI_CLK Bit Clock 2 Bursty Audio Input Bit Clock BDI_CLK is the bit clock input for the bursty serial audio data on BDI_DATA 141 33 Input BDI_DATA Compressed Audio Bursty Input Data BDI_DATA is the serial bursty audio data input that corresponds to the BDI_CLK serial bit clock 142 34 Input...

Page 62: ...ted most significant bit first on the first DAIn_SCLK after a DAIn_LRCLK transition and is valid on the rising edge of DAIn_SCLK For the left justified format the left subframe is presented when DAIn_LRCLK is high and the right subframe is presented when DAIn_LRCLK is low The left justified format can also be programmed for data to be valid on the falling edge of DAIn_SCLK Figure 5 3 Left justifie...

Page 63: ...ameters are defined as follows A Data Format B SCLK Polarity C LRCLK Polarity D DAI Mode Table 5 3 Table 5 4 Table 5 5 and Table 5 6 show the different values for each parameter as well as the hex message that needs to be sent to configure the port When creating the hardware configuration message only one hex message should be sent per parameter Table 5 3 Input Data Format Configuration Input Para...

Page 64: ...F0000 0x81400022 0x00001F00 0x81800023 0xFEFF0000 0x81400023 0x00001F00 0x81800024 0xFEFF0000 0x81400024 0x00001F00 2 DSD Normal Mode 0x81000020 0x00001F00 0x81000021 0x00001F00 0x81000022 0x00001F00 0x81000023 0x00001F00 0x81000024 0x00001F00 0x81000012 0x00001F00 0x81000014 0x00000000 0x81000013 0x83F01F0B 0x81000025 0x1008D11F Table 5 3 Input Data Format Configuration Input Parameter A Continue...

Page 65: ...1 Data Clocked in on SCLK Falling Edge 0x81400020 0x00200000 0x81400021 0x00200000 0x81400022 0x00200000 0x81400023 0x00200000 0x81400024 0x00200000 Table 5 5 Input LRCLK Polarity Configuration Input Parameter C C Value LRCLK Polarity Both DAI and CDI Port HEX Message 0 default LRCLK Low indicates Channel 0 i e Left 0x81800020 0xFFDFFFFF 0x81800021 0xFFDFFFFF 0x81800022 0xFFDFFFFF 0x81800023 0xFFD...

Page 66: ...AI Mode Configuration Input Parameter D D Value Description HEX Message 0 default DAI2_LRCLK SCLK Slave Compressed Data in on DAI_D4 0x81000025 0x1008D110 1 DAI1_LRCLK SCLK Slave Compressed Data in on DAI_D0 0x81000025 0x0000D190 2 DAI2_LRCLK SCLK Slave PCM Data in on DAI_D4 Routed to Center and LFE 0x81000025 0x1558E11F ...

Page 67: ...from up to 6 pins simultaneously 6 channels total DSD features include Six DSD Input Pins One Shared DSD_CLK for All Data Pins Supports 44 1 kHz 1 Fs 88 2 kHz 2 Fs and 176 4 kHz 4 Fs Sample Rates 6 1 1 DSD Pin Description Table 6 1 shows the mnemonic and pin description of the pins associated with the DSD port on CS4953xx 6 1 2 Supported DSD Functional Blocks Figure 6 1 below shows the functional ...

Page 68: ...igured for DSD Input CS4953xx Hardware Users Manual DS732UM7 Copyright 2008 Cirrus Logic Inc 6 2 Figure 6 1 DSD Port Block Diagram DSD_DATA0 DMA to Peripheral Bus DSD0 DSD_DATA1 DSD1 DSD_DATA2 DSD2 DSD_DATA3 DSD3 DSD_DATA4 DSD_CLK DSD4 DSD_DATA5 DSD5 ...

Page 69: ... a single clock domain The port supports data rates from 32 kHz to 192 kHz Each port can also be configured to provide a 32 kHz to 192 kHz S PDIF transmitter XMTA and XMTB as an output Figure 7 1 illustrates the DAO block diagram 7 1 Digital Audio Output Port Description 7 1 1 DAO Pin Description Figure 7 1 identifies the pins associated with the Digital Audio Output Ports DAO1 and DAO2 DAO_MCLK i...

Page 70: ...s and are typically configured for outputting two channels of I2S or left justified PCM data DAO2_DATA0 may also be configured to provide output for four or six channels of PCM data The DAO2_DATA3 XMTB pin can alternatively serve as an S PDIF transmitter output Figure 7 1 DAO Block Diagram 7 1 2 Supported DAO Functional Blocks As mentioned earlier in the previous section two DAO ports DAO1_DATA3 a...

Page 71: ...rising edge of DAO_SCLK The left subframe is presented when DAO_LRCLK is low and the right subframe is presented when DAO_LRCLK is high Figure 7 2 provides details on I2 S compatible maximum of 32 bits serial audio formats Figure 7 2 I2 S Compatible Serial Audio Formats Rising Edge Valid 7 1 3 2 Left Justified Format Figure 7 3 illustrates the left justified LJ format with a rising edge DAO_SCLK D...

Page 72: ... Clock Relationship C DAO_MCLK DAO_SCLK DAO_LRCLK Frequency Ratio D Data Format I2S Left Justified E DAO_LRCLK Polarity F DAO_SCLK Polarity Table 7 2 Table 7 3 Table 7 4 Table 7 5 Table 7 6 and Table 7 7 show the different values for each parameter as well as the hex message that needs to be sent to configure the port When creating the hardware configuration message only one hex message should be ...

Page 73: ...00002000 1 DAO_MCLK Slave DAO1_LRCLK Master DAO1_SCLK Master DAO2_LRCLK Master DAO2_SCLK Master DA02_LRCLK DA02_SCLK are driven by DA01_LRCLK DA01_SCLK 0x8180002C 0xFFFFDFFF 0x8180002D 0xFFFFDFFF Table 7 3 DAO1 DAO2 Clocking Relationship Configuration Parameter B B Value DAO1 DAO2 Clocking Relationship Hex Message 0 default DAO2 dependent on DAO1 clocks 0x8140002B 0x00002000 1 DAO2 independent of ...

Page 74: ...DAO2_SCLK 128 FS 0x8100003D 0x00017700 0x8100003E 0x00017700 0x8180002C 0xFFFFFF8F 0x8140002C 0x00000040 5 DAO_MCLK 512 FS DAO1_SCLK DAO_MCLK 8 64 FS DAO1_LRCLK DAO1_SCLK 64 FS DAO2_SCLK DAO_MCLK 8 64 FS DAO2_LRCLK DAO2_SCLK 64 FS 0x8100003D 0x00007713 0x8100003E 0x00007713 0x8180002C 0xFFFFFF8F 0x8140002C 0x00000020 6 DAO_MCLK 512 FS DAO1_SCLK DAO_MCLK 4 128 FS DAO1_LRCLK DAO1_SCLK 128 FS DAO2_SC...

Page 75: ...DAO_MCLK 2 192 FS DAO1_LRCLK DAO1_SCLK 192 FS DAO2_SCLK DAO_MCLK 2 192 FS DAO2_LRCLK DAO2_SCLK 192 FS 0x8100003D 0x00077201 0x8100003E 0x00077201 0x8180002C 0xFFFFFF8F 0x8140002C 0x00000050 Table 7 5 Output Data Format Configuration Parameter D D Value DAO Data Format Of DAO_DATA0 1 2 or DAO_DATA0 for Multichannel Modes Hex Message 0 default I2 S 32 bit 0x81000030 0x00000001 0x81000031 0x00000001 ...

Page 76: ...put DAO_LRCLK Polarity Configuration Parameter E E Value DAO_LRCLK Polarity Hex Message 0 default LRCLK Low indicates Left Subchannel 0x8140002C 0x00000700 0x8140002D 0x00000700 1 LRCLK Low indicates Right Subchannel 0x8180002C 0xFFFFFBFF 0x8140002C 0x00000300 0x8180002D 0xFFFFFBFF 0x8180002D 0x00000300 Table 7 7 Output DAO_SCLK Polarity Configuration Parameter F F Value DAO_SCLK Polarity Hex Mess...

Page 77: ...ream from input to the output for recording applications or as a PCM bypass for dual zone applications A soft reset is required when switching between any of the above modes Table 7 8 S PDIF Transmitter Pins Pin Name Pin Description LQFP 144 Pin LQFP 128 Pin Pin Type XMTA_IN S PDIF Input for XMTA mux The XMTA_IN S PDIF inputs is muxed with XMTA to allow switching the S PDIF output between the inte...

Page 78: ...ion CS4953xx Hardware Users Manual DS732UM7 Copyright 2008 Cirrus Logic Inc 7 10 Route XMTB_IN to DAO2_DATA3 XMTB 0x81000052 0x0000000b Disable DSP Bypass 0x81000052 0x00000003 Table 7 10 DSP Bypass Config DAO_SCLK Polarity Hex Message ...

Page 79: ...buffers and a single read buffer The P memory port has a single read buffer One of these buffers contains four 32 bit words 128 bits Every miss to the read buffer will cause the SDRAM controller to burst eight 16 bit reads on the SDRAM interface Figure 8 1 shows a block diagram of the SDRAM external memory control interface for the CS4953xx chip Figure 8 1 SDRAM Interface Block Diagram 8 2 Flash M...

Page 80: ... timing parameters have been chosen and tested to meet the requirements of Hynix HY57V641620HG H By default the SDRAM port is configured for 64 Mbits with 4 banks 12 rows and 8 columns with a RAS and CAS latency of 3 The physical interface of the Flash controller consists of 16 data pins EXT_D 15 0 20 address pins EXT_A 19 0 and 4 control pins EXT_CS1 EXT_CS2 EXT_OE EXT_WE The address and data pin...

Page 81: ...h Address 12 55 84 Output SD_BA0 EXT_A13a SDRAM Bank Address 0 Flash Address 13 75 104 Input SD_BA1 EXT_A141 SDRAM Bank Address 1 Flash Address 14 77 106 Input EXT_A15 Flash Address 15 82 111 Output EXT_A16 Flash Address 16 84 113 Output EXT_A17 Flash Address 17 85 114 Output EXT_A18 Flash Address 18 87 116 Output EXT_A19 Flash Address 19 88 117 Output SD_D0 EXT_D0 SDRAM Flash Bidirectional Data B...

Page 82: ... 49 78 BiDir SD_D9 EXT_D9 SDRAM Flash Bidirectional Data Bit 9 48 77 BiDir SD_D10 EXT_D10 SDRAM Flash Bidirectional Data Bit 10 46 75 BiDir SD_D11 EXT_D11 SDRAM Flash Bidirectional Data Bit 11 45 74 BiDir SD_D12 EXT_D12 SDRAM Flash Bidirectional Data Bit 12 43 72 BiDir SD_D13 EXT_D13 SDRAM Flash Bidirectional Data Bit 13 42 71 BiDir SD_D14 EXT_D14 SDRAM Flash Bidirectional Data Bit 14 41 70 BiDir ...

Page 83: ...HHHHHH Default 0x00000075 DynamictRP Configure the precharge command period Bit 31 4 0 Reserved Bit 3 0 Trp where 0x0 to 0xE n 1 DSP clk cycles 0xF 16 DSP clk cycles Example Trp 20nS HCLK 120Mhz Trp 20nS 120Mhz 1 1 4 0x2 0x81000062 0xHHHHHHHH Default 0x00000002 DynamictRAS Configure the active to precharge command period Bit 31 4 0 Reserved Bit 3 0 Tras where 0x0 to 0xE n 1 DSP clk cycles 0xF 16 D...

Page 84: ...l Trwl Bit 31 4 0 Reserved Bit 3 0 Tdal where 0x0 to 0xE n 1 DSP clk cycles 0xF 16 DSP clk cycles Example Twr 2 CLKs HCLK 120Mhz Twr 2 1 0x1 0x81000067 0xHHHHHHHH Default 0x00000001 DynamictRC Configure the active to active command time Bit 31 5 0 Reserved Bit 4 0 Trc where 0x0 to 0x1E n 1 DSP clk cycles 0x1F 16 DSP clk cycles Example Trc 65 nS HCLK 120Mhz Trc 65 nS 120 Mhz 1 7 8 1 0x7 0x81000068 ...

Page 85: ...to 0xE n 1 DSP clk cycles 0xF 16 DSP clk cycles Example Tmrd 1CLKs HCLK 120Mhz Tmrd 1 1 0x0 0x8100006C 0xHHHHHHHH Default 0x00000000 DynamicConfig0 Configure the active bank A to active bank B latency Bit 31 12 0 Reserved Bit 11 7 External bus address mapping Row Bank Column where 00001 16Mb 1Mx16 2 banks row length 11 column length 8 00101 64Mb 4Mx16 4 banks row length 12 column length 8 01001 12...

Page 86: ... SRAM_OEN_CYCLE HCLK 0x81000072 0xHHHHHHHH Default 0x00000000 StaticWaitRd0 Not Supported Single Word Read Cycle txmrdc Bit 31 5 0 Reserved Bit 4 0 SRAM_RD_CYCLE where 00000 to 11110 n 1 HCLK cycle for Read Cycle txmrdc SRAM_RD_CYCLE 1 HCLK 6 87ns 0x81000073 0xHHHHHHHH Default 0x0000001F StaticWaitWr0 Not Supported EXT_CS falling to EXT_WE rising txmcswa Bit 31 5 0 Reserved Bit 4 0 SRAM_WR_CYCLE w...

Page 87: ...Flash_OEN_CYCLE HCLK 0x81000079 0xHHHHHHHH Default 0x00000000 StaticWaitRd1 Single Word Read Cycle txmrdc Bit 31 5 0 Reserved Bit 4 0 Flash_RD_CYCLE where 00000 to 11110 n 1 HCLK cycle for Read Cycle txmrdc Flash_RD_CYCLE 1 HCLK 6 87ns 0x8100007A 0xHHHHHHHH Default 0x0000000A StaticWaitWr1 EXT_CS falling to EXT_WE rising txmcswa Bit 31 5 0 Reserved Bit 4 0 Flash_WR_CYCLE where 00000 to 11110 n 2 H...

Page 89: ... configuration is not preferred because the SDRAM and FLASH share a bus making routing more difficult Figure 9 7 is a typical connection diagram LQFP 144 showing SPI control with a serial FLASH SDRAM and up to 7 DACs This configuration uses the default settings for serial FLASH chip select pin 6 Figure 9 8 is a typical connection diagram LQFP 144 showing SPI control with a serial FLASH DSD Audio I...

Page 90: ...9 2 Typical Connection Diagrams CS4953xx Hardware Users Manual Figure 9 1 LQFP 144 I2 C Control Serial FLASH SDRAM 7 DACs For 16 Mbit parts SD_BA0 is used as a bank select For 64 Mbit and 128 Mbit parts SD_BA 1 0 is the 2 bit bank select Note ...

Page 91: ... 9 3 Typical Connection Diagrams CS4953xx Hardware Users Manual Figure 9 2 LQFP 144 SPI Control Serial FLASH SDRAM 7 DACs For 16 Mbit parts SD_BA0 is used as a bank select For 64 Mbit and 128 Mbit parts SD_BA 1 0 is the 2 bit bank select Note ...

Page 92: ... 9 4 Typical Connection Diagrams CS4953xx Hardware Users Manual Figure 9 3 LQFP 144 SPI Control Serial FLASH SDRAM 8 DACs For 16 Mbit parts SD_BA0 is used as a bank select For 64 Mbit and 128 Mbit parts SD_BA 1 0 is the 2 bit bank select Note ...

Page 93: ... 5 Typical Connection Diagrams CS4953xx Hardware Users Manual Figure 9 4 LQFP 144 I2 C Control Parallel Flash SDRAM 8 DACs For 16 Mbit parts SD_BA0 is used as a bank select For 64 Mbit and 128 Mbit parts SD_BA 1 0 is the 2 bit bank select Note ...

Page 94: ...9 6 Typical Connection Diagrams CS4953xx Hardware Users Manual Figure 9 5 LQFP 128 SPI Control Parallel Flash SDRAM 8 DACs For 16 Mbit parts SD_BA0 is used as a bank select For 64 Mbit and 128 Mbit parts SD_BA 1 0 is the 2 bit bank select Note ...

Page 95: ...ical Connection Diagrams CS4953xx Hardware Users Manual Figure 9 6 LQFP 128 I2C Control Serial FLASH DSD Audio Input SDRAM 7 DACs For 16 Mbit parts SD_BA0 is used as a bank select For 64 Mbit and 128 Mbit parts SD_BA 1 0 is the 2 bit bank select Note ...

Page 96: ...ical Connection Diagrams CS4953xx Hardware Users Manual Figure 9 7 LQFP 144 SPI Control Serial FLASH DSD Audio Input SDRAM 7 DACs For 16 Mbit parts SD_BA0 is used as a bank select For 64 Mbit and 128 Mbit parts SD_BA 1 0 is the 2 bit bank select Note ...

Page 97: ...ical Connection Diagrams CS4953xx Hardware Users Manual Figure 9 8 LQFP 144 SPI Control Serial FLASH DSD Audio Input SDRAM 7 DACs For 16 Mbit parts SD_BA0 is used as a bank select For 64 Mbit and 128 Mbit parts SD_BA 1 0 is the 2 bit bank select Note ...

Page 98: ...separate analog supply voltage required for the internal PLL VDDA These pins are described in the following tables and descriptions The DSP Core supply voltage pins require a nominal 1 8V The DSP I O supply voltage pins require a nominal 3 3V Table 9 1 Core Supply Pins LQFP 144 Pin LQFP 128 Pin Pin Name Pin Type Pin Description 10 42 VDD1 Input 1 8V DSP Core supply This powers all internal logic a...

Page 99: ...race A bulk capacitor of at least 10 uF is recommended for each power plane 9 2 2 PLL Filter 9 2 2 1 Analog Power Conditioning In order to obtain the best performance from the CS4953xx s internal PLL the analog power supply VDDA must be as noise free as possible A ferrite bead and two capacitors should be used to filter the VDDIO to generate VDDA This power scheme is shown in the Typical Connectio...

Page 100: ...equired to run the DSP and peripherals In A V Receiver designs that require low jitter clocks the XTI pin is typically connected to an external 12 288 MHz or 24 576 Mhz oscillator that is used throughout the system The CS4953xx has a built in crystal oscillator circuit A parallel resonant type crystal is connected between the XTI and XTO pins as shown in Figure 9 10 The value of C1 is specific to ...

Page 101: ...ld be pulled to VDD or GND using 10 kΩ resistors according to the specific control mode desired as shown in Table 2 1 Operation Modes on page 2 3 The following sections describe the pins used for the 5 control modes For example diagrams of system connection please see Section 9 1 Typical Connection Diagrams on page 9 1 For information on timing diagrams and messaging protocol to the CS4953xx see C...

Page 102: ...3xx Hardware User s Manual explains each communication mode in more detail Table 9 8 Reset Pin LQFP 144 Pin LQFP 128 Pin Pin Name Pin Type Pin Description 93 121 RESET Input Reset async active low Chip Reset Reset should be low at power up to initialize the DSP and to guarantee that the device is not active during initial power on stabilization periods Table 9 9 Hardware Strap Pins LQFP 144 Pin LQ...

Page 103: ...1 VDD4 GND4 SD_CS SD_A4 EXT_A4 SD_A5 EXT_A5 SD_A6 EXT_A6 SD_A7 EXT_A7 SD_A8 EXT_A8 SD_CLKEN SD_A9 EXT_A9 VDDIO4 GNDIO4 SD_CLKOUT SD_CLKIN SD_D10 EXT_D10 SD_D11 EXT_D11 SD_D12 EXT_D12 VDD3 GND3 SD_D13 EXT_D13 SD_D14 EXT_D14 SD_D15 EXT_D15 SD_DQM1 SD_D7 EXT_D7 SD_D6 EXT_D6 VDDIO3 GNDIO3 SD_D5 EXT_D5 SD_DQM0 SD_D4 EXT_D4 SD_D3 EXT_D3 SD_D2 EXT_D2 69 66 63 60 57 54 47 44 1 GPIO26 GPIO17 DAO1_DATA3 XMT...

Page 104: ...A6 EXT_A6 SD_A7 EXT_A7 SD_A8 EXT_A8 SD_CLKEN SD_A9 EXT_A9 VDDIO4 GNDIO4 SD_CLKOUT SD_CLKIN SD_D10 EXT_D10 SD_D11 EXT_D11 SD_D12 EXT_D12 VDD3 GND3 SD_D13 EXT_D13 SD_D14 EXT_D14 SD_D15 EXT_D15 SD_DQM1 SD_D7 EXT_D7 SD_D6 EXT_D6 VDDIO3 GNDIO3 SD_D5 EXT_D5 SD_DQM0 SD_D4 EXT_D4 SD_D3 EXT_D3 SD_D2 EXT_D2 95 90 85 80 75 70 GPIO17 DAO1_DATA3 XMTA GPIO15 DAO1_DATA1 HS1 DAO1_DATA0 HS0 DAO1_LRCLK DAI1_LRCLK D...

Page 105: ...t 1 DAO2_DATA3 2 XMTB 3 UART_TX_ENABLE 1 Digital Audio Output 3 2 Outputs IEC60958 61937 format bi phase mark encoded S PDIF data 3 Enable the UART_TX pin 3 3V 5V tol BiDir IN Y 6 38 GPIO20 General Purpose Input Output 1 DAO2_DATA2 2 EE_CS 1 Digital Audio Output 2 2 EEPROM Boot Chip Select 3 3V 5V tol BiDir IN Y 7 39 GPIO19 General Purpose Input Output 1 DAO2_DATA1 2 HS4 1 Digital Audio Output 1 2...

Page 106: ...age 3 3V PWR 19 51 DAO1_DAT A0 Digital Audio Output 0 HS0 Hardware Strap Mode Select 3 3V 5V tol BiDir IN 20 52 DAO1_SCL K PCM Audio Bit Clock 3 3V 5V tol BiDir IN Y 21 53 GNDIO1 I O ground 0V PWR 22 54 DAO1_LRC LK PCM Audio Sample Rate Clock 3 3V 5V tol BiDir IN Y 23 GPIO31 General Purpose Input Output UART_CLK UART Clock 3 3V 5V tol BiDir IN Y 24 55 VDD2 Core power supply voltage 1 8V PWR 25 GPI...

Page 107: ...lash Write Enable 3 3V 5V tol OUT 39 68 SD_D0 SDRAM Data Bit 0 EXT_D0 Flash Data Bit 0 3 3V 5V tol BiDir IN Y 40 69 SD_D15 SDRAM Data Bit 15 EXT_D15 Flash Data Bit 15 3 3V 5V tol BiDir IN Y 41 70 SD_D14 SDRAM Data Bit 14 EXT_D14 Flash Data Bit 14 3 3V 5V tol BiDir IN Y 42 71 SD_D13 SDRAM Data Bit 13 EXT_D13 Flash Data Bit 13 3 3V 5V tol BiDir IN Y 43 72 SD_D12 SDRAM Data Bit 12 EXT_D12 Flash Data ...

Page 108: ... 3 3V 5V tol OUT 56 85 SD_A11 SDRAM Address Bit 11 EXT_A11 Flash Address Bit 11 3 3V 5V tol OUT 57 86 GNDD3 Core ground 0V PWR 58 87 SD_A9 SDRAM Address Bit 9 EXT_A9 Flash Address Bit 9 3 3V 5V tol OUT 59 88 SD_A8 SDRAM Address Bit 8 EXT_A8 Flash Address Bit 8 3 3V 5V tol OUT 60 89 VDDIO4 I O power supply voltage 3 3V PWR 61 90 SD_A7 SDRAM Address Bit 7 EXT_A7 Flash Address Bit 7 3 3V 5V tol OUT 6...

Page 109: ...Address Bit 0 3 3V 5V tol OUT 73 100 VDDIO5 I O power supply voltage 3 3V PWR 74 103 SD_A10 SDRAM Address Bit 10 EXT_A10 Flash Address Bit 10 3 3V 5V tol OUT 75 104 SD_BA0 SDRAM Bank Address 0 EXT_A13 Flash Address Bit 13 3 3V 5V tol OUT 76 105 GNDIO5 I O ground 0V PWR 77 106 SD_BA1 SDRAM Bank Address 1 EXT_A14 Flash Address Bit 14 3 3V 5V tol OUT 78 107 SD_WE SDRAM Write Enable 3 3V 5V tol OUT 79...

Page 110: ...rpose Input Output 1 CSW_U 2 XMTB_IN 1 Channel status user data input 2 S PDIF Pass thru Input 3 3V 5V tol BiDir IN Y 93 121 RESET Chip Reset 3 3V 5V tol In 94 122 GNDIO6 I O ground 0V PWR 95 123 GPIO33 General Purpose Input Output SCP1_MOSI SPI Mode Master Data Output Slave Data Input 3 3V 5V tol BiDir IN Y 96 GPIO32 General Purpose Input Output 1 SCP1_CS 2 IOWAIT 1 SPI Chip Select 2 SRAM Hold Of...

Page 111: ... PCP_WR 2 PCP_DS 3 SCP2_CLK 1 Parallel Port Write Select Intel Mode 2 Parallel Port Data Strobe Motorola and Multiplexed Mode 3 SPI I2C Control Port Clock 3 3V 5V tol BiDir OD IN Y 1 GPIO38 General Purpose Input Output 1 SCP2_CLK 1 SPI I2 C Control Port Clock 3 3V 5V tol BiDir OD IN Y 104 GPIO39 General Purpose Input Output 1 PCP_CS 2 SCP2_CS 1 Parallel Port Chip Select Intel Motorola Multiplexed ...

Page 112: ...BiDir IN Y 108 GPIO41 General Purpose Input Output 1 PCP_IRQ 2 SCP2_IRQ 1 Parallel Control Port Data Ready Interrupt Request 2 Serial Control Port Data Ready Interrupt Request 3 3V 5V tol BiDir OD IN Y 109 GPIO9 General Purpose Input Output 1 PCP_A1 2 PCP_A9 1 Parallel Control Port Address Bit 1 2 Parallel Control Port Address Bit 9 3 3V 5V tol BiDir IN Y 4 GPIO9 General Purpose Input Output 1 SCP...

Page 113: ...P_D5 2 PCP_AD5 1 Parallel Control Port Data Bus 2 Parallel Control Port Multiplexed Address and Data Bus 3 3V 5V tol BiDir IN Y 115 GPIO4 General Purpose Input Output 1 PCP_D4 2 PCP_AD4 1 Parallel Control Port Data Bus 2 Parallel Control Port Multiplexed Address and Data Bus 3 3V 5V tol BiDir IN Y 116 9 GNDIO7 I O ground 0V PWR 117 GPIO3 General Purpose Input Output 1 PCP_D3 2 PCP_AD3 1 Parallel C...

Page 114: ...se Input Output 1 UART_CLK 1 UART Clock 3 3V 5V tol BiDir IN Y 122 15 GNDD7 Core ground 0V PWR 123 16 XTAL_OUT Buffered Reference Clock Input Crystal Oscillator Input 3 3V 5V tol OUT 124 17 XTI Reference Clock Input Crystal Oscillator Input 3 3V 5V tol ANA 125 18 XTO Crystal Oscillator Output 1 3 3V ANA 126 19 GNDA PLL ground 1 8V PWR 127 NC Do Not Connect on PCB 1 8V ANA 128 20 PLL_REF_ RES Curre...

Page 115: ...AI2_LRCLK 2 BDI_REQ 3 PCP_IRQ 4 PCP_BSY 1 PCM Audio Input Sample Rate Clock 2 Bursty Data Input Request 3 Parallel Control Port Data Ready Interrupt Request 4 Parallel Control Port Input Busy 3 3V 5V tol BiDir OD IN Y 32 GPIO42 General Purpose Input Output 1 DAI2_LRCLK 2 BDI_REQ 1 PCM Audio Input Sample Rate Clock 2 Bursty Data Input Request 3 3V 5V tol BiDir OD IN Y 141 33 GPIO43 General Purpose ...

Page 116: ...RT_TX_ENABLE 1 Digital Audio Output 3 2 Outputs IEC60958 61937 format bi phase mark encoded S PDIF data 3 Enable the UART_TX pin 3 3V 5V tol BiDir IN Y Table 9 10 Pin Assignments Continued LQFP 144 Pin LQFP 128 Pin Function 1 Default Description of Default Function Secondary Functions Description of Secondary Functions Pwr Type Reset State Pullup at Reset ...

Page 117: ... Assignments on page 9 17 for pins 138 and 142 Made same changes in Figure 9 11 for the 144 Pin LQFP pin layout drawing UM6 May 7 2008 Changed text in Figure Titles for Figure 9 1 Figure 9 2 Figure 9 4 and Figure 9 5 Modified Note 1 under Table 8 1 Change note regarding bank selection in Figures 9 1 to 9 7 Added new typical connection diagram in Figure 9 6 LQFP 128 I2 C Control Serial FLASH DSD Au...

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