32
DS1113F1
CS4399
4.6 Clock Output and Fractional-N PLL
The CLKOUT output is enabled by clearing PDN_CLKOUT.
Figure 4-14. CLKOUT Source Selection
Once enabled, CLKOUT is generated either from the internal crystal oscillator output (when used) or from the integrated
fractional-N PLL; it can be selected by CLKOUT_SEL. CLKOUT_DIV can be used to set /2, /3, /4, or /8 to divide the
selected clock source to targeted frequency.
4.6.1
Fractional-N PLL
The CS4399 has an integrated fractional-N PLL to support the clocking requirements of various applications. This PLL can
be enabled or disabled by clearing or setting PDN_PLL bit. The input reference clock for the PLL is signal on XTI/MCLK
pin (crystal-generated or external-feed).
4.6.2
Fractional-N PLL Internal Interface
shows how PLL operation can be configured.
Figure 4-15. Fractional-N PLL
Use
to calculate the PLL output frequency.
Equation 4-1. PLL Output Frequency Equation
PLL_REF source must be in range below:
PLL_REF Source
PLL_REF_PREDIV Input
Minimum
Maximum
MCLK/XIN pin
9.6 MHz
26 MHz
XTI/MCLK
PLL_OUT
CLKOUT
÷
CLKOUT_DIV
PLL
XTI/MCLK
PLL_OUT
PLL_DIV_INT p. 76
PLL_DIV_FRAC_0 p. 76
PLL_DIV_FRAC_1 p. 76
PLL_DIV_FRAC_2 p. 76
PLL_MODE p. 77
PLL_OUT =
PLL_REF
PLL_REF_PREDIV
×
1
PLL_OUT_DIV
PLL_D PLL_DIV_FRAC
or 1, selected by PLL_Mode
×
500
512