CS2200-CP
DS759F3
9
CONTROL PORT SWITCHING CHARACTERISTICS - SPI FORMAT
Inputs: Logic 0 = GND; Logic 1 = VD; C
L
= 20 pF.
Notes:
11.
t
spi
is only needed before first falling edge of CS after power is applied.
t
spi
= 0 at all other times.
12. Data must be held for sufficient time to bridge the transition time of CCLK.
13. For f
cclk
< 1 MHz.
Parameter
Symbol
Min
Max
Unit
CCLK Clock Frequency
f
ccllk
-
6
MHz
CCLK Edge to CS Falling
t
spi
500
-
ns
CS High Time Between Transmissions
t
csh
1.0
-
µs
CS Falling to CCLK Edge
t
css
20
-
ns
CCLK Low Time
t
scl
66
-
ns
CCLK High Time
t
sch
66
-
ns
CDIN to CCLK Rising Setup Time
t
dsu
40
-
ns
CCLK Rising to DATA Hold Time
t
dh
15
-
ns
Rise Time of CCLK and CDIN
t
r2
-
100
ns
Fall Time of CCLK and CDIN
t
f2
-
100
ns
Delay from Supply Voltage Stable to Control Port Ready
t
dpor
100
-
µs
t
r2
t
f2
t
dsu
t
dh
t
sch
t
scl
CS
CCLK
CDIN
t
css
t
csh
t
spi
t
dpor
VD
Figure 3. Control Port Timing - SPI Format (Write Only)
