Cirrus Logic CS2200-CP, Manual

Page: 7 / 26

CS2200-CP
DS759F3 7
AC ELECTRICAL CHARACTERISTICS
Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; T
A
= -10°C to +70°C (Commercial Grade);
T
A
= -40°C to +85°C (Automotive-D Grade); T
A
= -40°C to +105°C (Automotive-E Grade); C
L
= 15 pF.
Notes:
4.
5. f
CLK_OUT
is ratio-limited when f
CLK_IN
is below 72 Hz.
6. f
CLK_OUT
= 24.576 MHz; Sample size = 10,000 points;
AuxOutSrc[1:0]
= 11.
7. In accordance with AES-12id-2006 section 3.4.2. Measurements are Time Interval Error taken with 3rd
order 100 Hz to 40 kHz bandpass filter.
8. In accordance with AES-12id-2006 section 3.4.1. Measurements are Time Interval Error taken with 3rd
order 100 Hz Highpass filter.
9. The frequency accuracy of the PLL clock output is directly proportional to the frequency accuracy of the
reference clock.
Parameters Symbol Conditions Min Typ Max Units
Crystal Frequency
Fundamental Mode XTAL f
XTAL
RefClkDiv[1:0]
= 10
RefClkDiv[1:0]
= 01
RefClkDiv[1:0]
= 00
8
16
32
-
-
- 14
28
50 MHz
MHz
MHz
Reference Clock Input Frequency f
REF_CLK
RefClkDiv[1:0]
= 10
RefClkDiv[1:0]
= 01
RefClkDiv[1:0]
= 00
8
16
32
-
-
- 14
28
56 MHz
MHz
MHz
Reference Clock Input Duty Cycle D
REF_CLK
45 - 55 %
Internal System Clock Frequency f
SYS_CLK
8 14 MHz
PLL Clock Output Frequency f
CLK_OUT
( Note 5 ) 6 - 75 MHz
PLL Clock Output Duty Cycle t
OD
Measured at VD/2 45 50 55 %
Clock Output Rise Time t
OR
20% to 80% of VD - 1.7 3.0 ns
Clock Output Fall Time t
OF
80% to 20% of VD - 1.7 3.0 ns
Period Jitter t
JIT
( Note 6 ) - 70 - ps rms
Base Band Jitter (100 Hz to 40 kHz) (Notes 6 , 7 ) - 50 - ps rms
Wide Band JItter (100 Hz Corner) (Notes 6 , 8 ) - 175 - ps rms
PLL Lock Time - REF_CLK t
LR
f
REF_CLK
= 8 to 75 MHz - 1 3 ms
Output Frequency Synthesis Resolution ( Note 9 ) f
err
0 - ±0.5 ppm