Cirrus Logic CRYSTAL LAN CS890, Technical Reference Manual, Page: 16 / 80

16 AN83REV1
CS8900 Technical Reference Manual
2.2 Low Cost Ethernet Combo Card
Reference Design: CRD8900
This section describes the hardware design
of a low-cost, two-layer, full-featured Eth-
ernet solution intended for use in PC ISA-
bus. The goal of this design is a high degree
of application flexibility. Therefore, a num-
ber of features (BootPROM, AUI,
10BASE-2) are supported. An example of
this circuit is included in this Technical
Reference Manual.
2.2.1 General Description
The CS8900 ISA Ethernet controller is used
in this low cost, high performance ISA Eth-
ernet adapter card. This card has AUI,
10BASE-T and 10BASE-2 interfaces. The
very high level of integration of the
CS8900 results in a very low component
count. This makes it possible to design a
half height, two layered 16 bit ISA Ethernet
adapter card. Since the analog filters are
integrated on the CS8900, the card may be
compliant with FCC part 15 class (B)
compliant.
2.2.2 Board Design
A recommended component placement is
shown in Figure 2.2.1, and a recommended
board schematics are shown in Figures
2.2.2 to 2.2.7.
2.2.2.1 Crystal Oscillator
The CS8900, in the reference design, uses a
20.000 MHz crystal oscillator. The crystal
that is used in the design has a load capaci-
tance of 18 pF. The rest of the oscillator
circuitry is internal to the CS8900. Please
note that the crystal must be placed very
close to XTL1 and XTL2 pins of the
CS8900.
2.2.2.2 ISA Bus Interface
The ISA bus connections from the CS8900
can be easily routed to the ISA connector. If
the pin-out of the CS8900 is placed as
shown in Figure 2.2.1, there will be almost
no cross-over of the ISA signals. It is also
important to provide very clean and ade-
quate +5 V and ground connections to the
CS8900.
2.2.2.3 External Decode Logic
The CS8900 can be accessed in both I/O
and memory modes. The CS8900 internally
decodes the SA[0:19] address lines for the
lower 1M of memory. The reference design
uses an external decode logic to allow the
card to also decode decodes the upper 4
bits of the ISA address (LA[23:20]), thus
allowing the CS8900 to reside anywhere in
extended memory. This decode logic is im-
plemented using a 16R4 PAL at location U4.
This logic is configured by the CS8900. The
PAL then decodes the upper 4 bits of the ISA
address. Please refer to Section 2.3 of this
document for further information.
2.2.2.4 EEPROM
A 64 word (64 X16) EEPROM (location
U3) is used in the reference design to inter-
face with the CS8900. This EEPROM
holds the IEEE assigned Ethernet MAC
(physical) address for the board. (see Sec-
tion 3.2) The EEPROM also holds other
configuration information for the CS8900.