Cirrus Logic CRYSTAL LAN CS890, Technical Reference Manual, Page: 10 / 80

10 AN83REV1
CS8900 Technical Reference Manual
That is, it resides in the lower 1 Mega bytes
of address space.
To use the CS8900 in extended memory
address space requires an external address
decoder. This decoder decodes upper 4 bits
(LA[20:23]) of 24 bit ISA address lines. In
many embedded microprocessors such de-
codes are available though the microproc-
essors itself.
Please refer to Section 2.3.2.2 for further
information.
2.1.2.4 EEPROM
A 64 word (64 X16 bit) EEPROM (location
U3) is used in the reference design to inter-
face with the CS8900. This EEPROM
holds the IEEE assigned Ethernet MAC
(physical) address for the board (see Sec-
tion 3.3). The EEPROM also holds other
configuration information for the CS8900.
The last few bytes of the EEPROM are
used to store information about the hard-
ware configuration and software require-
ments.
In an embedded system, such as a PC, the
system CMOS RAM or any other non-
volatile memory can be used to store the
IEEE address and Ethernet configuration
information. In such a case an EEPROM is
not necessary for the CS8900, and the
CS8900 will respond to IO addresses 0300h
through 030Fh after a reset.
Please refer to the section 3.5 and 3.6 of the
CS8900 data sheet for information about
programming the EEPROM. Please refer
to the Section 3.0 of this document for in-
formation about EEPROM internal word
assignments.
2.1.2.5 LEDs
Many embedded systems do not require
LEDs for the Ethernet traffic. Therefore
this reference design does not implement
any LEDs. However, the CS8900 has di-
rect drives for the three LEDs. Please refer
to the data sheet for the CS8900 for a de-
scription of the LED functions available on
the CS8900.
2.1.2.6 10BASE-T Interface
The 10BASE-T interface for the CS8900 is
straight forward. Please refer to Figure
2.2.5 for connections and components of
this circuit. Transmit and receive signal
lines from the CS8900 are connected to an
isolation transformer at location T3. This
isolation transformer has a 1:1 ratio be-
tween the primary and the secondary
windings on the receive side, and a 1:
√
2
(1:1.41) ratio between the primary and the
secondary windings for the transmit lines.
Resistor R2 provides termination for the
receive lines. Resistors R4 and R5 are in
series with the differential pair of transmit
lines for impedance matching.
2.1.2.7 10BASE-2 and AUI Interfaces
As many embedded systems require only a
10BASE-T interface, this reference design
implements only the 10BASE-T interface.
However, should a user require a 10BASE-
2 or AUI interface, the CS8900 provides a
direct interface to the AUI. Please refer to
Section 2.2 of this document for details
about the AUI interface.