Cirrus Logic CDB5378 Manual Download

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CDB5378

DS639DB4

1.2.1

Default Jumper Settings

J27

Analog Input Selections

INA+

DAC_OUT-

INA-

DAC_OUT-

----------

INB-

----------

INB+

----------

INA+

DAC_BUF-

----------

INA-

DAC_BUF-

INB-

INB+

INA+

BNC_IN-

INA-

BNC_IN-

INB-

INB+

Table 1. Analog Input Default Jumper Settings

J40

Digital Filter RESET Selection

RST_PB

----------

RST_MC

RST_EXT

RST_CPLD

J58

Microcontroller RESET Selection

RST_PB

----------

RST_EXT

RST_CPLD

Table 2. RESET, SPI, SYNC Default Jumper Settings

J43

SPI Chip Select Input

EECS

----------

J56

SYNC Source Selection

SYNC_IO

----------

SYNC

Summary of Contents for CDB5378

Page 1: ...mic chip set Data sheets for the CS3301A CS5373A and CS5378 devices should be consulted when using the CDB5378 evaluation board Screw terminals connect an external differential geo phone or hydrophone sensor to the analog inputs of the measurement channel An on board test DAC creates precision differential analog signals for in circuit perfor mance testing without an external signal source The eva...

Page 2: ...ted circuits or other products of Cirrus This con sent does not extend to other copying such as copying for general distribution advertising or promotional purposes or for creating any work for resale CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH PERSONAL INJURY OR SEVERE PROP ERTY OR ENVIRONMENTAL DAMAGE CRITICAL APPLICATIONS CIRRUS PRODUCTS ARE NOT DESIGN...

Page 3: ...2 4 Delta Sigma Test DAC 19 2 2 5 Voltage Reference 20 2 3 Digital Hardware 20 2 3 1 Digital Filter 20 2 3 2 Interface CPLD 23 2 3 3 Digital Control Signals 25 2 3 4 Microcontroller 25 2 3 5 RS 485 Telemetry 27 2 3 6 UART Connection 29 2 3 7 External Connector 30 2 4 Power Supplies 30 2 4 1 Analog Voltage Regulators 30 2 4 2 Digital Voltage Regulators 31 2 5 PCB Layout 32 2 5 1 Layer Stack 32 2 5 ...

Page 4: ... 3 4 7 Harmonics 48 3 4 8 Spot Noise 48 3 4 9 Plot Error 48 3 5 Control Panel 49 3 5 1 DF Registers 50 3 5 2 DF Commands 50 3 5 3 SPI 50 3 5 4 Macros 51 3 5 5 GPIO 51 3 5 6 Customize 52 3 5 7 External Macros 52 4 BILL OF MATERIALS 53 5 LAYER PLOTS 56 6 SCHEMATICS 62 7 REVISION HISTORY 72 ...

Page 5: ... Diagram 13 Figure 2 Quad Group Routing of RC Filter Components 18 Figure 3 CPLD Default Signal Assignments 24 Figure 4 Differential Pair Routing 32 Figure 5 Quad Group Routing 33 Figure 6 Bypass Capacitor Placement 33 Figure 7 Dual row Headers with Shorts 34 ...

Page 6: ...ttings 6 Table 2 RESET SPI SYNC Default Jumper Settings 6 Table 3 VREF Power Supplies Default Jumper Settings 7 Table 4 Clock Default Jumper Settings 7 Table 5 RS 485 Default Jumper Settings 8 Table 6 DIP Switch Default Settings 8 Table 7 Screw Terminal Input Connectors 14 ...

Page 7: ...C Running Windows 2000 or XP with an Available USB Port Internet Access to Download the Evaluation Software 1 2 Hardware Setup To set up the CDB5378 evaluation board Set all jumpers and DIP switches to their default settings see next sections With power off connect the CDB5378 power inputs to the power supply outputs VA 12 V VA 12 V GND 0 V VD 12 V Connect the USB cable between the CDB5378 USB con...

Page 8: ...NB BNC_IN 17 18 INA BNC_IN 19 20 INA BNC_IN 21 22 INB BNC_IN 23 24 INB Table 1 Analog Input Default Jumper Settings J40 Digital Filter RESET Selection RST_PB 1 2 RST_MC 3 4 RST_EXT 5 6 RST_CPLD 7 8 J58 Microcontroller RESET Selection RST_PB 1 2 RST_EXT 3 4 RST_CPLD 5 6 7 8 Table 2 RESET SPI SYNC Default Jumper Settings J43 SPI Chip Select Input EECS 4 3 SS SS 2 1 SS J56 SYNC Source Selection SYNC_...

Page 9: ...election 3 3VD 1 2 2 5VD 3 4 EXT_VD 5 6 J10 VA Voltage Selection 2 5VA 1 2 GND 3 4 EXT_VA 5 6 Table 3 VREF Power Supplies Default Jumper Settings J19 Voltage Reference Jumpers VREF 4 3 VREF 2 1 J16 J17 J18 Digital Filter CPLD Microcontroller Input Clock Selections 32 768 MHz 1 2 16 384 MHz 3 4 8 192 MHz 5 6 4 096 MHz 7 8 2 048 MHz 9 10 1 024 MHz 11 12 CLK_EXT 13 14 15 16 Table 4 Clock Default Jump...

Page 10: ...J24 Clock Source CLK 1 2 CLK 3 4 CLK_I O 5 6 GND 7 8 J33 Clock Driver Enable GND 1 2 VD 3 4 J25 Sync Source SYNC 1 2 SYNC 3 4 SYNC_I O 5 6 GND 7 8 J34 Sync Driver Enable GND 1 2 VD 3 4 J15 I2C Data SDA 1 2 SDA 3 4 SDA 5 6 GND 7 8 S1 down up GAIN0 PLL0 1 2 GAIN1 PLL1 3 4 GAIN2 PLL2 5 6 MUX BOOT 7 8 S5 down up SP_SW1 1 2 LOGIC_GND 3 4 PWDN 5 6 7 8 Table 6 DIP Switch Default Settings ...

Page 11: ...e in stallation application will automatically be created Open the Volume1 sub folder and run setup exe If the Seismic Evaluation Software has been pre viously installed the uninstall wizard will automatically remove the previous version and you will need to run setup exe again Follow the instructions presented by the Cirrus Seismic Evaluation Installation Wizard The default in stallation location...

Page 12: ...271 Cirrus Seismic Evaluation GUI Installation Guide is available from the Cirrus Logic web site with step by step instructions on installing the USBXpress driver 1 3 4 Launching the Seismic Evaluation Software Important For reliable USB communication the USBXpress driver must be installed after the Seismic Evaluation Software installation but before launching the application The USBXpress driver ...

Page 13: ...Launch the evaluation software and apply power to CDB5378 Click OK on the About panel to get to the Setup panel On the Setup panel select Open Target on the USB Port sub panel When connected the Board Name and MCU code version will be displayed 1 4 1 Noise test Noise performance of the measurement channel can be tested as follows Set the controls on the Setup panel to match the picture ...

Page 14: ...ise statistics Verify the noise performance S N is 124 dB or better 1 4 2 Distortion Test Set the controls on the Setup panel to match the picture Once the Setup panel is set select Configure on the Digital Filter sub panel After digital filter configuration is complete click Capture to collect a data record Once the data record is collected the Analysis panel is automatically displayed Select Sig...

Page 15: ... blocks of the CDB5378 evaluation board include CS3301A Geophone Amplifier CS5373A Σ Modulator Test DAC CS5378 Digital Filter PLL Precision Voltage Reference Interface CPLD Microcontroller with USB RS 485 Transceivers Voltage Regulators Figure 1 CDB5378 Block Diagram ...

Page 16: ...he input selection jumpers 2 2 1 2 GUARD Output GND Connection By default CDB5378 uses the CS3301A differential geophone amplifier By replacing the amplifier and changing the pin 13 signal assignment J42 it is possible to use the CS3302A hydrophone amplifier in stead The CS3301A amplifier expects an MCLK clock input to pin 13 while the CS3302A amplifier pro duces an analog GUARD signal output to p...

Page 17: ...to 2000 V HBM 200 V MM JEDEC standard The small physical size of these ESD diodes restricts their current capacity to 10 mA For land applications using the CS3301A amplifier the INA input has a common mode and differential RC filter The common mode filter sets a low pass corner to shunt very high frequency components to ground with minimal noise contribution The differential filter sets a low pass...

Page 18: ...ied from the CDB5378 defaults depending on the sensor used Refer to the recom mended operating bias conditions for the selected sensor which are available from the sensor manufac turer Land Common Mode Filter Specification Value Common Mode Capacitance 10 nF 10 Common Mode Resistance 200 Ω Common Mode 3 dB Corner 6 dB octave 80 kHz 10 Land Differential Filter Specification Value Differential Capac...

Page 19: ...ce between pins on the back side of the PCB Converting between am plifier types requires carefully cutting the default short and installing a jumper A replacement amplifier can be requested as a sample from your local Cirrus Logic sales representative 2 2 2 2 Rough Fine Outputs OUTR OUTF The analog outputs of the CS3301A 02A differential amplifiers are split into rough charge and fine charge signa...

Page 20: ...mplifier The digital output from the modulator is an oversampled Σ bit stream 2 2 3 1 Rough Fine Inputs INR INF The modulator analog inputs are separated into rough and fine signals each of which has a differential anti alias RC filter to limit the input signal bandwidth Figure 2 Quad Group Routing of RC Filter Components INR INF INF INR INR INF INF INR Analog Signals Description INR INF Modulator...

Page 21: ...y 2 2 4 2 Buffered Output DAC_BUF The CS5373A test DAC has a buffered output DAC_BUF that is also routed to the input selection jump er This output is less sensitive to loading than the precision output and can be jumpered into either the INA or INB input without affecting performance The buffered output can also drive a sensor attached to the input screw terminals provided the sensor meets the im...

Page 22: ...ts 2 2 5 2 Common Mode Bias A buffered version of the voltage reference is created as a low impedance common mode bias source for the analog signal inputs The bias resistors connected between the buffered voltage reference and each analog signal input half depends on the sensor type and should be modified to match the sensor manu facturer recommendations 2 3 Digital Hardware 2 3 1 Digital Filter T...

Page 23: ...p resistor A four position DIP switch on CDB5378 S5 can connect 10k Ω pull down resistors to the GPIO 4 6 PLL 0 2 or GPIO7 BOOT pins so they will read low at reset Because the pin states are latched at reset GPIO pins can be programmed and used normally after reset without affecting the PLL and BOOT selections Detailed information about the PLL input clock and BOOT mode selections at reset can be ...

Page 24: ...rmation is initially written into the serial EEPROM by jumpering its chip select input EECS to the microcontroller chip select output SS and sending EEPROM programming commands and data from the PC evaluation software 2 3 1 3 Phase Locked Loop To make synchronous analog measurements throughout a distributed system a synchronous system clock is required to be provided to each measurement node For e...

Page 25: ...t http www xilinx com The hardware programmer interfaces with the Xilinx JTAG programming port J39 on CDB5378 Note that early versions of the Xilinx WebPack tools 7 1i SP1 and earlier have a bug in the JEDEC programming file for the CPLD included on CDB5378 and WebPack version 7 1i SP2 or later is required Included below is the default Verilog HDL file used by CDB5378 inside the interface CPLD Com...

Page 26: ...93 I pushbutton timebreak timeb_ext 98 I external timebreak timeb 52 O timebreak pulse to digital filter sync_pb 94 I pushbutton sync sync_mc 13 I sync from uC sync_ext 99 I external sync sync 53 O sync to CS5378 input signals input sck_mc mosi_mc ssz_mc input miso drdyz input sync_mc sync_pb sync_ext input timeb_pb timeb_mc timeb_ext wire sck_mc mosi_mc ssz_mc wire miso drdyz wire sync_pb sync_mc...

Page 27: ...of Silicon Laboratories http www silabs com Key features of the C8051F320 microcontroller are 8051 compatibility uses industry standard 8051 software development tools In circuit debugger software development on the target hardware Internal memory 16k flash ROM and 2k static RAM included on chip Multiple serial connections SPI USB I2C and UART High performance 25 MIPS maximum Low power 0 6 mA 1 MH...

Page 28: ... General Purpose I O 14 P2 4 CPLD4_MC General Purpose I O 15 P2 3 CPLD3_MC General Purpose I O 16 P2 2 CPLD2_MC General Purpose I O Pin Pin Name Assignment Description 17 P2 1 CPLD1_MC General Purpose I O 18 P2 0 CPLD0_MC General Purpose I O 19 P1 7 BYP_EN I2C bypass switch control 20 P1 6 SDA_DE I2C data driver enable 21 P1 5 SCL I2C clock in out 22 P1 4 SDA I2C data in out 23 P1 3 SS_MCz SPI chi...

Page 29: ...ontroller uses an internally generated 12 MHz clock for compatibility with USB standards 2 3 4 5 Timebreak Signal By default the C8051F320 microcontroller sends the TIMEB_MC signal to the digital filter for the first col lected sample of a data record By default 100 initial samples are skipped during data collection to ensure the CS5378 digital filters are fully settled and the timebreak signal is...

Page 30: ...be synchronized to the network at the transmitter since no local timing adjustment is available A microcontroller hardware connection is made when the SYNC_IO signal is received over the dedicated RS 485 twisted pair and detected by a microcontroller interrupt The microcontroller can then use an in ternal counter to re time the SYNC_MC signal output to the digital filter SYNC input as required A m...

Page 31: ...depending how the telemetry system is to be implemented Dynamic address assignment uses daisy chained I2C connections to assign an address to each mea surement node Once a node receives an address it enables the I2C bypass switches to the next node so it can be assigned an address Static address assignment has a serial number assigned to each node during manufacturing When placed in the network th...

Page 32: ...spect to ground Each input also has 100 uF bulk ca pacitance for bypassing and to help settle transients and another 0 01 uF capacitor to bypass high fre quency noise 2 4 1 Analog Voltage Regulators Linear voltage regulators create the positive and negative analog power supply voltages to the analog components on CDB5378 These regulate the EXT_VA and EXT_VA power supply inputs to create the VA and...

Page 33: ... EXT_VA is supplied to the digital voltage regulators to create the VD and VCORE power supplies The VD and VCORE power supplies on CDB5378 can be jumpered to use regulated 3 3 V or 2 5 V power supplies or an unregulated direct connection to EXT_VD Extreme care must be taken when using a direct connection to EXT_VD not to exceed the maximum specified power supply voltages of the digital components ...

Page 34: ...e to leave the system No separate analog ground is required since analog signals on CDB5378 are differentially routed CDB5378 layer 3 is dedicated for power supply routing Each power supply net includes at least 100 µF bulk capacitance as a charge well for settling transient current loads CDB5378 layer 4 is dedicated as a digital routing layer 2 5 2 Differential Pairs Analog signal routes on CDB53...

Page 35: ...e INF and INF traces 2 5 3 Bypass Capacitors Each device power supply pin includes 0 1 µF bypass capacitors placed as close as possible to the pin on the back side of the PCB Each power supply net includes at least 100 µF bulk capacitance as a charge well for transient current loads Figure 5 Quad Group Routing INR INF INF INR INR INF INF INR Figure 6 Bypass Capacitor Placement TOP BOTTOM ...

Page 36: ...ween the dual row pins can be carefully cut to isolate the device signals from the rest of the PCB to permit wiring changes to the existing route To restore the previous connection install a jumper to short across the dual row pins Signals taken off the PCB should not be wired directly from the dual row header pins as there is no clean path for the signal return current Instead install a connector...

Page 37: ...clipboard Print Analysis Screen Prints the full Analysis panel including statistics fields Print Analysis Graph Prints only the graph from the Analysis panel High Resolution Printing Prints using the higher resolution of the printer Low Resolution Printing Prints using the standard resolution of the screen Quit Exits the application software Setup Displays the Setup Panel Analysis Displays the Ana...

Page 38: ...8 38 DS639DB4 3 2 About Panel The About panel displays copyright information for the Cirrus Seismic Evaluation software Click OK to exit this panel Select Help Ö About from the menu bar to display this panel ...

Page 39: ...anel The Setup panel initializes the evaluation system to perform data acquisition It consists of the following sub panels and controls USB Port Digital Filter Analog Front End Test Bit Stream Gain Offset Data Capture External Macros ...

Page 40: ...nalysis and Control panel access becomes unavailable in the menu bar The evaluation software constantly monitors the USB connection status and automatically disconnects if the target board is turned off or the USB cable is unplugged Board Name Displays the type of target board currently connected MCU code version Displays the version number of the microcontroller code on the connected target board...

Page 41: ... the output filter stage from the digital filter Sinc output FIR1 output FIR2 output IIR 1st order output IIR 2nd order output or IIR 3rd order output can be selected FIR2 output provides full decimation of the modulator data FIR Coeff Selects the on chip FIR coefficient set to use in the digital filter Linear phase or min imum phase FIR coefficients can be selected IIR Coeff Selects the on chip I...

Page 42: ... the CS3301A 02A amplifiers An internal termination external INA inputs or external INB inputs can be selected DAC Mode Selects the operational mode of the CS5373A test DAC The test DAC operational modes are AC dual output OUT BUF AC precision output OUT only AC buffered output BUF only DC common mode output DC Common DC differential output DC Diff or AC common mode output AC Common The test DAC c...

Page 43: ...ed The Configure button writes the new configuration to the target board and then enables the data Capture button Control Description DAC Quick Set Automatically sets test bit stream options Mode selects sine or impulse output mode Freq selects the test signal frequency for sine mode and Gain selects the test signal amplitude in dB Interpolation Manual control for the data interpolation factor of ...

Page 44: ... calibration results are automatically written to the OFFSET registers and remain there even after offset calibration is disabled Control Description Gain Displays the digital filter GAIN register Offset Displays the digital filter OFFSET register Read Reads values from the GAIN and OFFSET registers Write Writes values to the GAIN and OFFSET registers USEGR Enables gain correction When enabled out...

Page 45: ...ed to the collected data set Used to ensure proper analysis of discontinuous data sets Bandwidth Limit Hz Sets the frequency range over which to perform analysis used to exclude higher fre quency components Default value of zero performs analysis for the full Nyquist fre quency range Full Scale Code Defines the maximum positive full scale 24 bit code from the digital filter Used during FFT noise a...

Page 46: ...macros m2 mac etc External Macro buttons can be re named on the panel by right clicking on them The button name will change but the macro associated with that button is always saved as m1 mac m2 mac etc in the macros subdirectory The External Macro button names are stored in the file Mnames txt also in the macros subdirectory External Macros allow up to eight macros to be accessed quickly without ...

Page 47: ... 3 4 Analysis Panel The Analysis panel is used to display the analysis results on collected data It consists of the following controls Test Select Statistics Plot Enable Cursor Zoom Refresh Harmonics Spot Noise Plot Error ...

Page 48: ...en plots sample occur rence vs sample value Only valid for noise data since sine wave data varies over too many codes to plot as a histogram Signal FFT Runs an FFT on the collected data set and then plots frequency magnitude vs fre quency Statistics are calculated using the largest frequency magnitude bin as a full scale signal reference Noise FFT Runs an FFT on the collected data set and then plo...

Page 49: ...nction the Cursor is used to select the corners of the area to zoom Control Description Time Domain Max Maximum code of collected data set Min Minimum code of collected data set Histogram Max Maximum code of collected data set Min Minimum code of collected data set Mean Mean of collected data set Std Dev Standard Deviation of collected data set Variance Variance of collected data set Signal FFT S ...

Page 50: ...ghts the fundamental and harmonic bins used to calculate the Signal FFT statistics HARMONICS highlighting helps to understand the source of any Signal FFT plot errors 3 4 8 Spot Noise The Spot Noise control labeled dB or nV is only visible during a Noise FFT analysis and selects the units used for plotting the graph either dB Hz or nV rtHz The dB Hz plot applies the Full Scale Code value from the ...

Page 51: ... Panel The Control panel is used to write and read register settings and to send commands to the digital filter It consists of the following sub panels and controls DF Registers DF Commands SPI1 Macros GPIO Customize External Macros ...

Page 52: ...escription Address Selects a digital filter register Data Contains the data written to or read from the register Read Initiates a register read Write Initiates a register write Control Description Command Selects the command to be written to the digital filter Write Data 1 Contains the SPI1DAT1 data to be written to the digital filter Write Data 2 Contains the SPI1DAT2 data to be written to the di...

Page 53: ...lects special commands that can be performed Data Sets the register data value for the inserted macro command Also sets the parame ter value for special commands Clear Clears the currently displayed macro Load Loads a previously saved macro Save Saves the currently displayed macro Macros can be saved with unique names or can be saved as External Macros Insert Inserts a macro command at the selecte...

Page 54: ...n them The button name will change but the macro associated with that button is always saved as m1 mac m2 mac etc in the macros subdirectory The External Macro button names are stored in the file Mnames txt also in the macros subdirectory External Macros allow up to eight macros to be accessed quickly without having to load them into the Mac ros sub panel on the Control panel These External Macros...

Page 55: ...LU SQUIRES ELEC INC 15 130 00009 Z1 A JACK BAN SOLDR TERM NYL INS YLW NPb 1 J7 JOHNSON COMPONENTS 108 0907 001 REQUIRES BINDING POST HOOK UP WIRE L 1 500 X 0 250T X 0 250T TYPE E 24 19 BLU SQUIRES ELEC INC 16 130 00014 Z1 A JACK BAN SOLDR TERM NYL INS BLK NPb 1 J8 JOHNSON COMPONENTS 108 0903 001 REQUIRES BINDING POST HOOK UP WIRE L 1 500 X 0 250T X 0 250T TYPE E 24 19 BLU SQUIRES ELEC INC 17 130 0...

Page 56: ...A RES 100 OHM 1 10W 1 NPb 0603 FILM 3 R60 R63 R69 DALE CRCW0603100RFKEA ECO000541 46 000 00002 Z1 A NO POP RES NPb 0603 0 R61 NO POP NP RES 0603 DO NOT POPULATE 47 020 01016 Z1 A RES 1k OHM 1 10W 1 NPb 0603 FILM 4 R64 R65 R66 R67 DALE CRCW06031K00FKEA 48 120 00011 Z1 A SWT 4 POS DIP RAISED NPb SPST 2 S1 S5 GRAYHILL 76SB04T 49 120 00002 Z1 A SWT SPST 130G 0 1 5mm TACT ESD NPb 3 S2 S3 S4 ITT INDUSTR...

Page 57: ... BLK NPb 28 MOLEX 15 29 1025 69 603 00133 Z1 C ASSY DWG PWA CDB5378 Z NPb RE F CIRRUS LOGIC 603 00133 Z1 70 240 00133 Z1 C PCB CDB5378 Z NPb 1 CIRRUS LOGIC 240 00133 Z1 71 600 00133 Z1 C1 SCHEM CDB5378 Z NPb RE F CIRRUS LOGIC 600 00133 Z1 72 300 00025 Z1 A SCREW 4 40X5 16 PH MACH SS NPb 8 XMH1 XMH2 XMH3 XMH4 XMH5 XMH6 XMH7 XMH8 BUILDING FASTENERS PMSSS 440 0031 PH 73 110 00028 Z1 A CON BNC PCB RCP...

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Page 74: ...639DB4 7 REVISION HISTORY Revision Date Changes DB1 FEB 2006 Initial Release DB2 APR 2006 Minor correction DB3 AUG 2006 Corrected PDF printing problem DB4 NOV 2007 Updated differential op amp from CS3301 to CS3301A ...

Page 75: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Cirrus Logic CDB5378 ...

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