Cirrus Logic CDB5378, Manual

Page: 26 / 75

CDB5378
26 DS639DB4
cdb5378.v
///////////////////////////////////////////////////////////////////////////
// MODULE: CDB5378 top module
//
// FILE NAME: Top module for connecting CS5378 to C8051F320
// VERSION: 1.0
// DATE: November 27, 2007
// COPYRIGHT: Cirrus Logic, Inc.
//
// CODE TYPE: Register Transfer Level
//
// DESCRIPTION: This module includes assignments for signals between
// the serial port of Rodney and the SLAB micro.
//
///////////////////////////////////////////////////////////////////////////
module cdb5378(
sck_mc, // 5 I serial clock from printer port
miso_mc, // 6 O serial output
mosi_mc, // 7 I serial input
ssz_mc, // 8 I slave select (active low)
drdyz_mc, // 9 O data ready (active low)
sck, // 61 O serial clock
miso, // 60 I serial output
mosi, // 58 O serial input
ssz, // 57 O slave select (active low)
drdyz, // 56 I data ready (active low)
timeb_mc, // 14 I timebreak pulse (active high)
timeb_pb, // 93 I pushbutton timebreak
timeb_ext, // 98 I external timebreak
timeb, // 52 O timebreak pulse to digital filter
sync_pb, // 94 I pushbutton sync
sync_mc, // 13 I sync from uC
sync_ext, // 99 I external sync
sync); // 53 O sync to CS5378
//////////////////
// input signals
//////////////////
input sck_mc, mosi_mc, ssz_mc;
input miso, drdyz;
input sync_mc, sync_pb, sync_ext;
input timeb_pb, timeb_mc, timeb_ext;
wire sck_mc, mosi_mc, ssz_mc;
wire miso, drdyz;
wire sync_pb, sync_mc, sync_ext;
wire timeb_pb, timeb_mc, timeb_ext;
//////////////////
//output signals
//////////////////
output miso_mc, drdyz_mc;
output sck, mosi, ssz;
output sync;
Page 1
output timeb;
wire miso_mc, drdyz_mc;
wire sck, mosi, ssz;
wire sync;
wire timeb;
///////////////////////
// signal assignments
///////////////////////
assign mosi = ssz_mc? 1'bz:mosi_mc;
assign ssz = ssz_mc? 1'bz:ssz_mc;
assign sck = (ssz_mc & drdyz )? 1'bz:sck_mc;
assign miso_mc = miso;
assign drdyz_mc = drdyz;
assign sync = sync_pb | sync_mc | sync_ext;
assign timeb = timeb_pb | timeb_mc | timeb_ext;
endmodule
Figure 3. CPLD Default Signal Assignments