Copyright
©
Cirrus Logic, Inc. 2008
(All Rights Reserved)
Evaluation Board for the CS43L21
Features
MUX’d Analog Output
–
Stereo RCA Output (w/Optional Load or
LPF)
–
Stereo Headphone Jack
–
Mono Speaker Driver w/Banana Posts
8 kHz to 96 kHz S/PDIF Interface
–
CS8415 Digital Audio Receiver
I/O Stake Headers
–
External Control Port Accessibility
–
External DSP Serial Audio I/O Accessibility
Independent, Regulated Supplies
1.8 V to 3.3 V Logic Interface
Hardware Control
–
11 Pre-Defined Switch Settings
FlexGUI S/W Control - Windows
®
Compatible
–
Pre-Defined & User-Configurable Scripts
Layout and Grounding Recommendations
Description
The CDB43L21 evaluation board is an excellent means
for evaluating the CS43L21 DAC. Evaluation requires a
digital signal source, analog analyzer, and power sup-
plies. Optionally, a Windows
PC-compatible computer
may be used to evaluate the CS43L21 in Software
Mode.
System timing can be provided by the CS8415, by the
CS43L21 with supplied master clock, or by an I/O stake
header with a DSP connected.
RCA phono jacks are provided for the CS43L21 analog
outputs. 1/8th inch jacks are also available for head-
phone output. Digital data input is available via RCA
phono or optical connectors to the CS8415.
The Windows software provides a Graphical User Inter-
face (GUI) to make configuration of the CDB43L21
easy. The software communicates through the PC’s se-
rial port/USB to configure the control port registers so
that all the features of the CS43L21 can be evaluated.
The evaluation board may also be configured to accept
external timing and data signals for operation in a user
application during system development.
ORDERING INFORMATION
CDB43L21
Evaluation Board
Analog Output
(Line + Headphone)
Software Mode
Control Port
CS43L21
S/PDIF Input
(CS8415)
Clocks/Data Header
I²C/SPI Header
FPGA
Oscillator
(socket)
Reset
MCLK
Reset
Reset
MCLK
Reset
Hardware Mode
Switches
JANUARY '08
DS723DB1
CDB43L21
Summary of Contents for CDB43L21
Page 16: ...16 DS723DB1 CDB43L21 7 CS43L21 SCHEMATICS Figure 10 CS43L21 and Analog I O Schematic Sheet 1 ...
Page 17: ...DS723DB1 17 CDB43L21 Figure 11 S PDIF I O Schematic Sheet 2 ...
Page 18: ...18 DS723DB1 CDB43L21 Figure 12 FPGA Schematic Sheet 3 ...
Page 19: ...DS723DB1 19 CDB43L21 Figure 13 Level Shifters I O Stake Header Schematic Sheet 4 ...
Page 20: ...20 DS723DB1 CDB43L21 Figure 14 Control Port I O Schematic Sheet 5 ...
Page 21: ...DS723DB1 21 CDB43L21 Figure 15 Power Schematic Sheet 6 ...
Page 22: ...22 DS723DB1 CDB43L21 8 CDB43L21 LAYOUT Figure 16 Silk Screen CDB43L21 CS43L21 CS43L21 CS43L21 ...
Page 23: ...DS723DB1 23 CDB43L21 Figure 17 Top Side Layer ...
Page 24: ...24 DS723DB1 CDB43L21 Figure 18 Bottom Side Layer ...
