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DS773DB1

CDB42L55

JMP

LABEL

PURPOSE

POSITION

FUNCTION SELECTED

J31

Selects source of voltage for the

VL supply

*+1.8V

Voltage source is +1.8 V regulator.

+2.5V

Voltage source is +2.5 V regulator.

+3.3V

Voltage source is +3.3 V regulator.

+1.8VB

Voltage source is +1.8V from battery.

J36

VCP

Selects source of voltage for the

VCP supply

*+1.8V

Voltage source is +1.8 V regulator.

+2.5V

Voltage source is +2.5 V regulator. .

+1.8VB

Voltage source is +1.8V from battery.

J25

Selects source of voltage for the

VA supply

*+1.8V

Voltage source is +1.8 V regulator.

+2.5V

Voltage source is +2.5 V regulator. .

+1.8VB

Voltage source is +1.8V from battery.

J28

VLDO

Selects source of voltage for the

VLDO supply

*+1.8V

Voltage source is +1.8 V regulator.

+2.5V

Voltage source is +2.5 V regulator. .

+1.8VB

Voltage source is +1.8V from battery.

J52
J74
J53
J48

VLDO

VA
VL

VCP

Current Measurement

*SHUNTED

Ω

series resistor is shorted.

OPEN

Ω

series resistor in power supply path.

J11

Shunt to RCA

Provides RCA reference to GND

*SHUNTED

AIN2B and AIN2A RCAs are given a ground ref-
erence.

Shunt to RCA

Provides RCA reference to GND

*SHUNTED

AIN1B and AIN1A RCAs are given a ground ref-
erence.

J22

HP Detect

Selects how the HP_Detect pin on

CS42L55is driven

1 - 2

HPDETECT is driven by FPGA/GUI.

*2 - 3

HPDETECT is driven by HP Jack line when a
stereo connection is inserted in J1.

1.8V Buck Input

Selects power supply source for

+1.8VB

1 - 2

1.8VB is derived from external input.

*2 - 3

1.8VB is derived from AAA batteries.

J12

HPOUTA

Selects test load from HPOUTA

1 - 2

Ω

load selected for HPOUTA.

2 - 3

Ω

load selected for HPOUTA.

HPOUTB

Selects test load from HPOUTB

1 - 2

Ω

load selected for HPOUTB.

2 - 3

Ω

load selected for HPOUTB.

HPOUTA

HPOUTA(LPF)

Connects or removes LPF for

HPOUTA

1 - 2

No filtered output selected for HPOUTA.

*2 - 3

RC filtered output selected for HPOUTA.

HPOUTB

HPOUTB(LPF)

Connects or removes LPF for

HPOUTB

1 - 2

No filtered output selected for HPOUTB.

*2 - 3

RC filtered output selected for HPOUTB.

J34

Board Power

Selects source of Board Power

1 - 2

Board powered from ex5V source con-
nected to TP9/TP10.

*2 - 3

Board powered from USB.

*Default factory settings

Table 2. Jumper Settings

Summary of Contents for CDB42L55

Page 1: ...g can be provided by the CS8416 S PDIF Re ceiver by the CS42L55 supplied with a master clock or via an I O stake header with a DSP connected RCA connectors are provided for CS42L55 analog inputs and HP Line outputs A 1 8 inch audio jack is provided for head phone stereo out Digital I O connections are available via RCA phono or optical connectors to the CS8416 and CS8406 S PDIF Rx and Tx The CDB42...

Page 2: ...ate Converter Rx SRC from CS42L55 6 2 5 FPGA 6 2 6 Oscillator 7 2 7 CS42L55 Audio CODEC 7 3 CONFIGURATION OPTIONS 8 3 1 S PDIF or PSIA In to Analog Out 8 3 2 Analog In to S PDIF or PSIA Out 9 4 SOFTWARE MODE CONTROL 10 4 1 Board Configuration Tab 11 4 2 CODEC Configuration Tab 12 4 3 Analog Input Volume Tab 13 4 4 DSP Engine Tab 14 4 5 Analog Output Volume Tab 15 4 6 Register Maps Tab 16 5 SYSTEM ...

Page 3: ...Digital In to HP Out 60 dBFS 21 Figure 23 FFT Digital In to HP Out no input 21 Figure 24 Freq Response Digital In to HP Out 21 Figure 25 Fade to Noise Linearity Digital In to HP Out 21 Figure 26 FFT Crosstalk Digital In to HP Out 0 dBFS 22 Figure 27 THD N vs Freq Digital In to Line Out 22 Figure 28 THD N vs Amplitude Digital In to Line Out 22 Figure 29 THD N vs Volume Digital In to Line Out 22 Fig...

Page 4: ...s FlexGUI software Figure 1 Quick Start Board Layout Set desired jumper settings for J12 J4 J2 and J3 1 2 3 4 5 6 7 Set jumper settings for VL to 3 3V and VCP VLDO and VA to 1 8V J48 J53 J52 J74 J7 and J11 should be shunted Set Board Power setting to USB Left pins on J109 and J104 should be shunted Provide digital inputs to the board either through the S PDIF optical or RCA connectors or through t...

Page 5: ... For a detailed explanation on software controls refer to Section 4 on page 10 Alternatively the I C interface to the CS42L55 can be directly accessed through an I O header J109 to accept external timing and data signals in a user application during system development 2 2 Power Power is supplied to the evaluation board through either the 5 0 V test points or the VBUS supply from the USB NOTE The m...

Page 6: ...ure 38 on page 26 and a discussion of the digital audio inter face can be found in the CS8406 data sheet Configuration of the CS8406 is made using controls in the Board Configuration tab of the Cirrus FlexGUI software Section 3 Configuration Options on page 8 and Section 4 Software Mode Control on page 10 provide configuration examples and software details 2 4 2 CS8421 Sample Rate Converter Rx SRC...

Page 7: ...t The device footprint on the board will accommodate full or half can sized oscillators 2 7 CS42L55 Audio CODEC A complete description of the CS42L55 U1 can be found in the CS42L55 product data sheet The CS42L55 is configured using the Cirrus FlexGUI The device configuration registers are accessible via the Register Maps tab of the Cirrus FlexGUI software This tab provides low level control of eac...

Page 8: ...he digital clock and data signal routing on the board as shown in Figure 2 The quick setup scripts provided in the software assume that a 24 000 MHz on board oscillator is populated in Y1 A S PDIF input must be provided as the S PDIF Tx CS8406 uses the RMCK signal from the S PDIF Rx CS8416 for synchronization in this configuration Figure 2 S PDIF or PSIA In to Analog Out PSIA Tx J78 TX SCLK TX LRC...

Page 9: ...ck and data signal routing on the board as shown in Figure 3 The quick setup scripts provided in the software assume that a 24 000 MHz on board oscillator is populated in Y1 A S PDIF input must be provided as the S PDIF Tx CS8406 uses the RMCK signal from the S PDIF Rx CS8416 for synchronization in this configuration Figure 3 Analog In to S PDIF or PSIA Out CS42L55 SCLK LRCK Rx SRC CS8421 PSIA Rx ...

Page 10: ...ult reset state 4 Refresh the GUI by clicking on the Update button The default state of all registers are now visible For standard set up 5 Set up the signal routing in the Board Configuration tab as desired 6 Set up the CS42L55 in the CODEC tabs as desired 7 Begin evaluating the CS42L55 For quick set up the CDB42L55 may alternatively be configured by loading a predefined sample script file 8 On t...

Page 11: ... Quick Setups section FPGA Routing Includes controls to setup the FPGA for using the S PDIF or the PSIA test interface and for setting up clock and signal routing for CS42L55 master slave mode CS8416 S PDIF Receiver Control Register controls for setting up the CS8416 CS8406 S PDIF Transmitter Control Register controls for setting up the CS8406 CS8421 SRC Control Register controls for the receive a...

Page 12: ...iption of each control group is outlined below See the CS42L55 data sheet for complete register descriptions Power Control Register controls for powering down each device within the CODEC ADC Configuration Controls for the input MUXs PGA MUX s and high pass filter settings Serial Port Configuration Controls for all settings related to the serial I O data and clocks on the board Update Reads all re...

Page 13: ...of each con trol group is outlined below a description of each register is included in the CS42L55 data sheet Digital Volume Control Digital volume controls and adjustments ADC output ALC Configuration Configuration settings for the Automatic Level Control ALC Analog Volume Control Analog volume controls and adjustments PGA and MIC amps Noise Gate Configuration All configuration settings for the n...

Page 14: ...sociated control A description of each control group is outlined below a description of each register is included in the CS42L55 data sheet Digital Volume Control Configures the volume gain of the ADC mix or the PCM data from the serial data input SDIN in the DSP Tone Control Sets the corner frequencies and the volume gain of the treble and bass shelving filters in the DSP engine Beep Generator Co...

Page 15: ...h control group is outlined below register descriptions are in the CS42L55 data sheet Class H Controls Controls for defining the digital and analog advisory volume charge pump frequency and adaptive power supply mode for the Class H amplifier Headphone Line Amplifiers Controls for configuring mutes and for setting the volume of the signal out of the headphone line amplifier Also allows one to conf...

Page 16: ...es can be modified bit wise or byte wise Left clicking on a particular register accesses that register and shows its contents at the bottom The user can change the register con tents by using the push buttons by selecting a particular bit and typing in the new bit value or by selecting the register in the map and typing in a new hex value Figure 9 Register Maps Tab CS42L55 ...

Page 17: ...ng the FPGA U5 MICRO JTAG J110 Input Output I O for programming the microcontroller U84 AP PSIA Transmitter J78 Input Digital Outputs to CS42L55 typically derived from an Audio Precision Pro grammable Serial Interface Adapter AP PSIA Receiver J40 Output Digital I O from CS42L55 typically derived from an Audio Precision Pro grammable Serial Interface Adapter MCLK SCLK LRCK ADC SDOUT DAC SDIN J77 J4...

Page 18: ... GND SHUNTED AIN2B and AIN2A RCAs are given a ground ref erence J7 Shunt to RCA Provides RCA reference to GND SHUNTED AIN1B and AIN1A RCAs are given a ground ref erence J22 HP Detect Selects how the HP_Detect pin on CS42L55is driven 1 2 HPDETECT is driven by FPGA GUI 2 3 HPDETECT is driven by HP Jack line when a stereo connection is inserted in J1 J5 1 8V Buck Input Selects power supply source for...

Page 19: ...e CS42L55 is determined by the value of the capacitor on the FILT pin Larger capacitor values yield significant improvement in THD N at low frequencies Fig 10 shows the THD N vs frequency performance measured with a 2 2 µF capacitor 100 60 95 90 85 80 75 70 65 d B F S 20 20k 50 100 200 500 1k 2k 5k 10k Hz 100 60 95 90 85 80 75 70 65 d B F S 60 10 50 40 30 20 dBr Figure 10 THD N vs Freq Analog In t...

Page 20: ...0k Hz 3 0 2 5 2 1 5 1 0 5 d B F S 20 20k 50 100 200 500 1k 2k 5k 10k Hz Figure 16 Freq Response Analog In to Digital Out Figure 17 Fade to Noise Linearity Analog In to Digital Out 40 40 30 20 10 0 10 20 30 d B F S 125 0 100 75 50 25 dBr 100 60 95 90 85 80 75 70 65 d B r A 20 20k 50 100 200 500 1k 2k 5k 10k Hz Figure 18 THD N vs Freq Digital In to HP Out Figure 19 THD N vs Amplitude Digital In to H...

Page 21: ...100 200 500 1k 2k 5k 10k Hz 140 0 120 100 80 60 40 20 d B r A 20 20k 50 100 200 500 1k 2k 5k 10k Hz Figure 22 FFT Digital In to HP Out 60 dBFS Figure 23 FFT Digital In to HP Out no input 140 0 120 100 80 60 40 20 d B r A 20 20k 50 100 200 500 1k 2k 5k 10k Hz 3 3 2 1 0 1 2 d B r A 20 20k 50 100 200 500 1k 2k 5k 10k Hz 40 40 30 20 10 0 10 20 30 d B r A 125 0 100 75 50 25 dBFS Figure 24 Freq Response...

Page 22: ...85 80 75 70 65 d B r A 100 0 80 60 40 20 dBFS 120 50 110 100 90 80 70 60 d B r A 60 0 50 40 30 20 10 dBr A Figure 28 THD N vs Amplitude Digital In to Line Out Figure 29 THD N vs Volume Digital In to Line Out Master Volume Digital Line Volume Analog 140 0 120 100 80 60 40 20 d B r A 20 20k 50 100 200 500 1k 2k 5k 10k Hz 140 0 120 100 80 60 40 20 d B r A 20 20k 50 100 200 500 1k 2k 5k 10k Hz Figure ...

Page 23: ...ure 33 FFT Crosstalk Digital In to Line Out 0 dBFS 140 0 120 100 80 60 40 20 d B r A 20 20k 50 100 200 500 1k 2k 5k 10k Hz 3 3 2 1 0 1 2 d B r A 20 20k 50 100 200 500 1k 2k 5k 10k Hz 40 40 30 20 10 0 10 20 30 d B r A 125 0 100 75 50 25 dBFS Figure 34 Freq Response Digital In to Line Out Figure 35 Fade to Noise Linearity Digital In to Line Out ...

Page 24: ...pplicable Fs from 24 MHz oscillator PLL I C for all applicable devices LDO VL VCP VLDO VA MUX 3 3 V VL only Circuit Break for External System Interface PCM Clocks Data I C Clocks Data I O Stake Headers for Audio Precision s Programmable Serial Interface Adapter PSIA I O SMA Connectors for External System Interface Tri state Buffers SRC Rx SRC Tx S PDIF Rx S PDIF Tx Stereo Input 1 Stereo Input 2 St...

Page 25: ...DS773DB1 25 CDB42L55 8 CDB42L55 SCHEMATICS Figure 37 CS42L55 Analog I O Schematic Sheet 1 ...

Page 26: ...26 DS773DB1 CDB42L55 Figure 38 S PDIF Digital Interface Schematic Sheet 2 ...

Page 27: ...DS773DB1 27 CDB42L55 Figure 39 PLL oscillator and external I O connections Schematic Sheet 3 ...

Page 28: ...28 DS773DB1 CDB42L55 Figure 40 Microcontroller and FPGA Schematic Sheet 4 ...

Page 29: ...DS773DB1 29 CDB42L55 Figure 41 Power Schematic Sheet 5 ...

Page 30: ...30 DS773DB1 CDB42L55 9 CDB42L55 LAYOUT Figure 42 Silk Screen ...

Page 31: ...DS773DB1 31 CDB42L55 Figure 43 Top Side Layer ...

Page 32: ...32 DS773DB1 CDB42L55 Figure 44 GND Layer 2 ...

Page 33: ...DS773DB1 33 CDB42L55 Figure 45 Power Layer 3 ...

Page 34: ...34 DS773DB1 CDB42L55 Figure 46 Bottom Side Layer ...

Page 35: ...DS773DB1 35 CDB42L55 10 REVISION HISTORY Revision Changes DB1 Initial Release ...

Page 36: ... your organization with respect to Cirrus integrated circuits or other products of Cirrus This consent does not extend to other copying such as copying for general distribution advertising or promotional purposes or for creating any work for resale CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH PERSONAL INJURY OR SEVERE PROP ERTY OR ENVIRONMENTAL DAMAGE CRIT...

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