Cirrus Logic CDB4272 Page 17 Manual Download | Manualshive

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Summary of Contents for CDB4272

Page 1: ...aluate the CS4272 in control port mode System timing can be provided by the CS4272 by the CS8416 phase locked to its S PDIF input by an I O stake header or by an on board oscillator RCA phono jacks are provided for the CS4272 analog outputs Bal anced XLR jacks are provided for the CS4272 analog inputs Digital data I O is available via RCA phono or op tical connectors to the CS8416 and CS8406 Micro...

Page 2: ...s consent does not extend to other copying such as copying for general distribution advertising or promotional purposes or for creating any work for resale An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this ma terial and controlled under the Foreign Exchange and Foreign Trade Law is to be exported...

Page 3: ... Schematic Sheet 4 19 Figure 10 CS8416 S PDIF Receiver Schematic Sheet 5 20 Figure 11 CS8406 S PDIF Transmitter Schematic Sheet 6 21 Figure 12 Board Setup Schematic Sheet 7 22 Figure 13 PCM Header Schematic Sheet 8 23 Figure 14 Control Port Schematic Sheet 9 24 Figure 15 Power Schematic Sheet 10 25 Figure 16 Component Placement and Reference Designators 26 Figure 17 Top Layer 27 Figure 18 Bottom L...

Page 4: ...terface format selection of either Left Justified or I2 S can be made via the control port GUI or via the I2S LJ position on switch S1 see Table 2 for switch control options 1 3 CS8416 Digital Audio Receiver The operation of the CS8416 receiver see Figure 10 and a discussion of the digital audio interface are included in the CS8416 data sheet The CS8416 converts the input S PDIF data stream into P...

Page 5: ...2 For a complete sche matic of the analog input buffer printed on the PCB refer to Figure 19 1 6 Analog Outputs The CS4272 analog output is routed through a differential to single ended unity gain low pass filter which is AC coupled to an RCA phono jack see Figure 9 The analog output filter on the CDB4272 has been designed to add flexibility when evaluating the CS4272 DAC out puts The output filte...

Page 6: ... size resis tors are used Similar to the parallel resistors in the resistor divider pad these are used to provide sufficient power handling capability in order to accommodate the high signal levels output from the instrumentation amplifier stage When not using the instrumentation amplifi er these resistors may all be replaced with 1 10 W 0805 size resistors The attenuation provided by the output m...

Page 7: ...tput from the differential amp used in LPF configuration 2 For a design utilizing only LPF configuration 1 the levels on that leg are suf ficiently low and a much smaller value capacitor can be used 22 µF 1 7 Stand Alone Control Switch S1 allows stand alone hardware signal routing and configuration of the CDB4272 See Table 2 for a list of the various options available After changing settings using...

Page 8: ...r is placed across J34 the header J32 may be used as an input When set as an input the control signals on J32 are routed to the cor responding control pins on the CS4272 and external control signals may be applied 1 10 Power Power must be supplied to the evaluation board through at least three binding posts 5 0 V J1 18 0 V J6 and 18 0 V J7 Jumper J10 allows the user to connect the VA supply of the...

Page 9: ...X COAX J12 Output CS8406 digital audio output via coaxial cable TX OPT J18 Output CS8406 digital audio output via optical cable PC Port J31 Input Output Parallel connection to PC for SPI I2C control port signals and sys tem configuration PCM HEADER J26 Input Output I O for Clocks Data 8416 SDOUT J24 Output CS8416 serial data output SDOUT 8406 SDIN J17 Input External data source for CS8406 SDIN EXT...

Page 10: ... Single Speed Mode with De emphasis Single Speed Mode w out De emphasis Double Speed Mode Quad Speed Mode J11 J19 Selects LED or Mute Circuit for AOUTA AOUTB 1 2 Mute Circuit Affects Analog Output Mute Circuit Disconnected LED displays xMUTEC status J10 Selects source of voltage for the VA supply 5V ADJ Voltage source is J1 5 0 V binding post Voltage source is J5 VA binding post J9 Selects source ...

Page 11: ...nnection attach the required user supplied flat rib bon cable to the header with the power supplies turned off 9 With all cables and connections in place turn on the power supplies to the board Turn on supplies in this order 5 V 18 V 18 V 10 Press and release the RESET switch S2 The LED D5 will illuminate as long as S2 is depressed indicating a reset condition Once S2 is released the LED should tu...

Page 12: ...should be set to HI 3 Assert a reset by pressing the RESET button S2 4 Apply a S PDIF input signal to the optical connector OPT1 The converted signal should appear at the analog output jacks AOUTR and AOUTL 5 Apply an analog input signal to the analog input jacks AINR and AINL The converted sig nal should appear at the S PDIF TX output jacks J12 and J18 ...

Page 13: ...ng and formats To apply changes to the board the Send Board Setup button must be pressed after making changes within the Board Setup box The CS4271 2 Setup box allows configuration of the internal registers of the CS4272 Chang es made within this box will be reflected immediately When in I2C mode the Update button will read the registers of the CS4272 and update the CS4271 2 Setup box to match Cli...

Page 14: ...ledge Error The control port of the CS4272 requires the presence of an MCLK signal for correct opera tion Because of this if the board is set up to receive MCLK from a source that isn t actively providing the signal a no acknowledge error may result This means that the GUI is expecting an acknowledgement from the CS4272 but isn t receiving it If this occurs ensure that the appropriate source of MC...

Page 15: ...K RMCK OSCLK OLRCK MCLK I O LRCK I O SCLK I O SDIN In SDOUT Out RMCK Disable Subclock Dir MCLK Dir Canned Oscillator OMCK SDOUT SDIN 4272 SDIN Source 8416 SDOUT 8406 SDIN Source SDIN 8406 SDIN SDOUT HW SW HW SW HW SW HW SW SW XTI XTO CS4272 Figure 5 Clock and Data Routing ...

Page 16: ...CDB4272 16 5 SCHEMATICS AND LAYOUT Figure 6 Hierarchy Schematic Sheet 1 ...

Page 17: ...CDB4272 17 Figure 7 CS4272 Schematic Sheet 2 ...

Page 18: ...CDB4272 18 Figure 8 Analog Input Schematic Sheet 3 ...

Page 19: ...CDB4272 19 Figure 9 Analog Output Schematic Sheet 4 ...

Page 20: ...CDB4272 20 Figure 10 CS8416 S PDIF Receiver Schematic Sheet 5 ...

Page 21: ...CDB4272 21 Figure 11 CS8406 S PDIF Transmitter Schematic Sheet 6 ...

Page 22: ...CDB4272 22 Figure 12 Board Setup Schematic Sheet 7 ...

Page 23: ...CDB4272 23 Figure 13 PCM Header Schematic Sheet 8 ...

Page 24: ...CDB4272 24 Figure 14 Control Port Schematic Sheet 9 ...

Page 25: ...CDB4272 25 Figure 15 Power Schematic Sheet 10 ...

Page 26: ...CDB4272 26 Figure 16 Component Placement and Reference Designators ...

Page 27: ...CDB4272 27 Figure 17 Top Layer ...

Page 28: ...CDB4272 28 Figure 18 Bottom Layer ...

Page 29: ...CDB4272 29 6 APPENDIX Complete Analog Input Buffer Schematic Figure 19 Complete Analog Input Buffer Schematic ...

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