CDB4272
12
2.2.1Verifying Board Operation:
1) If connected, disconnect the PC parallel cable.
2) Set all positions on S1 to LO, with the exception of M0 which should be set to HI.
3) Assert a reset by pressing the RESET button (S2).
4) Apply a S/PDIF input signal to the optical connector (OPT1). The converted signal should
appear at the analog output jacks AOUTR and AOUTL.
5) Apply an analog input signal to the analog input jacks AINR and AINL. The converted sig-
nal should appear at the S/PDIF TX output jacks (J12 and J18).
Summary of Contents for CDB4272
Page 16: ...CDB4272 16 5 SCHEMATICS AND LAYOUT Figure 6 Hierarchy Schematic Sheet 1 ...
Page 17: ...CDB4272 17 Figure 7 CS4272 Schematic Sheet 2 ...
Page 18: ...CDB4272 18 Figure 8 Analog Input Schematic Sheet 3 ...
Page 19: ...CDB4272 19 Figure 9 Analog Output Schematic Sheet 4 ...
Page 20: ...CDB4272 20 Figure 10 CS8416 S PDIF Receiver Schematic Sheet 5 ...
Page 21: ...CDB4272 21 Figure 11 CS8406 S PDIF Transmitter Schematic Sheet 6 ...
Page 22: ...CDB4272 22 Figure 12 Board Setup Schematic Sheet 7 ...
Page 23: ...CDB4272 23 Figure 13 PCM Header Schematic Sheet 8 ...
Page 24: ...CDB4272 24 Figure 14 Control Port Schematic Sheet 9 ...
Page 25: ...CDB4272 25 Figure 15 Power Schematic Sheet 10 ...
Page 26: ...CDB4272 26 Figure 16 Component Placement and Reference Designators ...
Page 27: ...CDB4272 27 Figure 17 Top Layer ...
