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OG_STD-302S-429M_v11e

Circuit Design, Inc.

5

OPERATION GUIDE

Receiver part

Item

MIN

TYP

MAX

Remarks

Receiver type

Double superheterodyne

1st IF frequency

MHz

21.7

2nd IF frequency

kHz

450

Maximum input level

dBm

10

BER (0 error/2556 bits)

*1

dBm

-108

-115

PN 9 4800bps

BER (1 % error)

*2

dBm

-120

PN 9 4800bps

Sensitivity 12dB/ SINAD

dBm

-120

fm1 k/ dev 2kHz CCITT

Spurious response rejection

*3

dB

70

1 st Mix, 2 signal method, 1 % error

55

2 nd Mix, 2 signal method, 1 % error

Adjacent CH selectivity

*3

dB

50

+/- 12.5kHz,
2 signal method, 1 % error

Intermodulation

*4

dB

50

2 signal method, 1 % error

DO output level

V

0

2.8

L = GND H = 2.8 V

RSSI rising time

ms

30

50

CH shift of 12.5 kHz (from PLL setup)

50

70

When power ON (from PLL setup)

Time until valid Data-out

*5

ms

50

100

CH shift of 12.5 kHz (from PLL setup)

70

120

When power ON (from PLL setup)

Spurious radiation

dBm

-60

-54

Conducted 50 ohm

RSSI

mV

300

350

400

With -97 dBm at 429.5 MHz

190

240

290

With -113 dBm at 429.5 MHz

Specifications are subject to change without prior notice

Notice

The time required until a stable DO is established may get longer due to the possible frequency drift
caused by operation environment changes, especially when switching from TX to RX, from RX to TX
and changing channels. Please make sure to optimize the timing. The recommended preamble is more
than 20 ms.

Antenna connection is designed as pin connection.

RF output power, sensitivity, spurious emission and spurious radiation levels may vary with the trace
used between the RF pin and the coaxial connection. Please make sure to verify those parameters
before use.

The feet of the shield case should be soldered to a wide GND pattern to avoid any change in
characteristics.

Notes about the specification values

*1

BER: RF level where no error per 2556 bits is confirmed with the signal of PN9 and 4800 bps.

*2

BER (1 % error) : RF level where 1% error per 2556 bits is confirmed with the signal of PN9 and 4800 bps.

*3

Spurious response, CH selectivity: Jamming signal used in the measurement is unmodulated.

*4

Intermodulation: Ratio between the receiver input level with BER 1% and the signal level (PN9 4800 bps)

added at the points of 'Receiving frequency - 200 kHz ' + ' Receiving frequency -100kHz' with which BER
1% is achieved.

*5

Time until valid Data-out : Valid DO is determined at the point where Bit Error Rate meter starts detecting

the signal of 4800bps, 1010repeated signal.

All specifications are specified based on the data measured in a shield room using the PLL setting controller
board prepared by Circuit Design.

Measuring equipment:
SG=ANRITUS communication analyzer MT8802
Spectrum analyzer = ANRITSU MS2830A
BER measure = ANRITSU MP1201G

Summary of Contents for STD-302

Page 1: ...cal and radio knowledge for setup and operation To ensure proper and safe operation please read this operation guide thoroughly prior to use Please keep this operation guide for future reference CIRCU...

Page 2: ...CIFICATIONS STD 302S 429 MHz 4 PIN DESCRIPTION 6 BLOCK DIAGRAM 9 DIMENSIONS 10 PLL IC CONTROL 11 PLL IC control 11 How to calculate the setting values for the PLL register 12 Method of serial data inp...

Page 3: ...gned to meet the basic specifications of Japanese ARIB STD T67 standard however it has not been certified for conformity with the technical regulations Users are required to perform the procedures for...

Page 4: ...illation type PLL controlled VCO Frequency stability 20 to 60 C ppm 4 4 Reference frequency at 25 C TX RX switching time ms 15 20 DI DO Channel step kHz 12 5 Data rate bps 2400 4800 DO DI Max pulse wi...

Page 5: ...anging channels Please make sure to optimize the timing The recommended preamble is more than 20 ms Antenna connection is designed as pin connection RF output power sensitivity spurious emission and s...

Page 6: ...TXSEL I TX select terminal GND TXSEL active To enable the transmitter circuits connect TXSEL to GND and RXSEL to OPEN or 2 8 V RXSEL I RX select terminal GND RXSEL active To enable the receiver circu...

Page 7: ...g input Interface voltage H 2 8 V L 0 V LD O PLL lock unlock indicator terminal Lock H 2 8 V Unlock L 0 V RSSI O Received Signal Strength Indicator terminal DO O Data output terminal Interface voltage...

Page 8: ...rmittent communication possible 8 429 2625 9 429 2750 10 429 2875 11 429 3000 12 429 3125 13 429 3250 14 429 3750 15 429 3875 16 429 3625 17 429 3750 18 429 3875 19 429 4000 20 429 4125 21 429 4250 22...

Page 9: ...OPERATION GUIDE OG_STD 302S 429M_v11e Circuit Design Inc 9 BLOCK DIAGRAM STD 302S 429MHz...

Page 10: ...OPERATION GUIDE OG_STD 302S 429M_v11e Circuit Design Inc 10 DIMENSIONS...

Page 11: ...equency is set externally by the controlling IC STD 302S has control terminals CLK LE DATA for the PLL IC and the setting data is sent to the internal register serially via the data line Also STD 302S...

Page 12: ...4 note fcomp fosc R Also this PLL IC operates with the following R N A and M relational expressions R fosc fcomp Equation 5 N INT n M Equation 6 A n M x N Equation 7 INT integer portion of a division...

Page 13: ...at this phase The PLL IC which operates as shown in the block diagram in the manual shifts the data to the 19 bit shift register and then transfers it to the respective latch counter register by judgi...

Page 14: ...n operating in the same channel a new PLL setting is not necessary it can receive data within 5 ms of switching 1 For data transmission if the RF channel to be used for transmission is set while still...

Page 15: ...el is not changed 5 ms 4 40 ms CPU Power on CH Data 5 5 ms 5 ms Check LD signal Check LD signal Normal status Status immediately after power comes on Channel change No channel change 4 2 Initialize th...

Page 16: ...614 509 38 18 429 3875 407 6875 407 6875 32615 509 39 19 429 4000 407 7000 407 7000 32616 509 40 20 429 4125 407 7125 407 7125 32617 509 41 21 429 4250 407 7250 407 7250 32618 509 42 22 429 4375 407 7...

Page 17: ...50 407 9250 32634 509 58 38 429 6375 407 9375 407 9375 32635 509 59 39 429 6500 407 9500 407 9500 32636 509 60 40 429 6625 407 9625 407 9625 32637 509 61 41 429 6750 407 9750 407 9750 32638 509 62 42...

Page 18: ...he PLL setting control board prepared by Circuit Design TEST DATA RSSI output level characteristic Measurement frequency 429 MHz Modulation unmodulated 25 C 5 C Signal level dBm RSSI mV 130 130 120 17...

Page 19: ...to the radio module Communication performance will be affected by the surrounding environment so communication tests should be carried out before actual use Ensure that the power supply for the radio...

Page 20: ...OG_STD 302S 429M_v11e Circuit Design Inc 20 OPERATION GUIDE REVISION HISTORY Version Date Description Remark 1 0 Jan 2015 1 1 Apr 2015 RSSI graph was revised P 18...

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