Theory of Operation
6-3
Figure 6-4 shows the digital stage structure.
FPGA
DSP
Memory
Linear
Regulator
+1.26VD
+3.3VD
+5VD
DGND
Isolated APG
Keyboard
K Board
U Board
RS232/RS485
USB,System BUS
G Board
GPIB
Ethernet
Z Board
Fan signal
A Board
AC_Fault signal
C Board
F Board
Driver signal
SCR driver signal
+1.2VD
D Board
Figure 6-4
6.2
Function Description
6.2.1
I/P (PFC) Stage
1.
The input stage is a bridge rectifier to rectify the 3-phase power source to DC.
2.
The way input stage inhibits inrush current is to connect the input circuit to a 40
resistor in series during power-on to charge the input capacitor. Turn on the SCR after
a few seconds and bypass this current limit resistor.