CC1000
SWRS048A Page 14 of 55
Figure 5. Configuration registers read operation
Parameter
Symbol
Min
Max
Units
Conditions
PCLK, clock
frequency
F
CLOCK
- 10 MHz
PCLK low
pulse
duration
T
CL,min
50
ns
The minimum time PCLK must be low.
PCLK high
pulse
duration
T
CH,min
50
ns
The minimum time PCLK must be high.
PALE setup
time
T
SA
10
-
ns
The minimum time PALE must be low before
negative edge of PCLK.
PALE hold
time
T
HA
10
-
ns
The minimum time PALE must be held low after
the
positive
edge of PCLK.
PDATA setup
time
T
SD
10
-
ns
The minimum time data on PDATA must be ready
before the negative edge of PCLK.
PDATA hold
time
T
HD
10
-
ns
The minimum time data must be held at PDATA,
after the negative edge of PCLK.
Rise time
T
rise
100
ns
The maximum rise time for PCLK and PALE
Fall time
T
fall
100
ns
The maximum fall time for PCLK and PALE
Note: The set-up- and hold-times refer to 50% of VDD.
Table 2. Serial interface, timing specification
PCLK
Address
Read mode
6
5
4
3
2
1
0
R
7
6
5
4
3
2
1
0
Data byte
PALE
PDATA
