Casio CE-6800, Service Manual

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8. LH28F016SCT-L95A
ADDRESS INPUTS: Inputs for addresses during read and write operations.
Addresses are internally latched during a write cycle. A
0
-A
20
INPUT
DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles;
outputs data during memory array. status register, and identifier code read
cycles. Data pins float to high-impedance when the chip is deselected or
outputs are disabled. Data is internally latched during a write cycle. DQ
0
-DQ
7
INPUT/
OUTPUT
BLOCK ERASE, BYTE WRITE, LOCK-BIT CONFIGURATION POWER
SUPPLY:For erasing array blocks, writing bytes, or configuring lock-bits. With
V
PP
≤
V
PPLK
, memory contents cannot be altered, Block erase, byte write, and
lock-bit configuration with an invalid V
PP
(see DC Characteristics) produce
spurious results and should not be attempted.
V
PP
SUPPLY
DEVICE POWER SUPPLY:Internal detection configures the device for 2.7 V,
3.3 V or 5 V operation. To switch from one voltage to another, ramp V
CC
down
to GND and then ramp V
CC
to the new voltage. Do not float any power pins.
With V
CC
≤
V
LKO
, all write attempts to the flash memory are inhibited. Device
operations at invalid V
CC
voltage (see DC Characteristics) produce spurious
results and should not be attempted. Block erase, byte write and lock-bit
configuration operations with V
CC
< 3.0 V are not supported.
V
cc
SUPPLY
CHIP ENABLE: Activates the device's control logic, input buffers, decoders,
and sense amplifiers. CE#-high deselects the device and reduces power
consumption to standby levels. CE# INPUT
WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and
data are latched on the rising edge of the WE# pulse. WE# INPUT
READY/BUSY#: Indicates the status of the internal WSM. When low, the
WSM is performing an internal operation (block erase, byte write, or lock-bit
configuration). RY/BY#-high indicates that the WSM is ready for new
commands, block erase is suspended, and byte write is inactive, byte write is
suspended, or the device is in deep power-down mode. RY/BY# is always
active and does not float when the chip is deselected or data outputs are
disabled. RY/BY# OUTPUT
RESET/DEEP POWER-DOWN: Puts the device in deep power-down mode
and resets internal automation. RP#-high enabies normal operation. When
driven low. RP# inhibits write operations which provides data protection during
power transitions. Exit from deep power-down sets the device to read array
mode. RP# at V
HH
enables setting of the master lock-bit and enables
configuration of block lock-bits when the master lock-bit is set. RP# = V
HH
overrides block lock-bits theredy enabling block erase and byte write
operations to locked memory blocks. Block erase, byte write. or lock-bit
configuration with V
HH
<RP#<V
HH
produce spurious results and should not be
attempted.
RP# INPUT
OUTPUT ENABLE: Gates the device's output during a read cycle. OE# INPUT
GROUND: Do not float any ground pins. GND SUPPLY
NO CONNECT: Lead is not internal connected: it may be driven or floated. NC
Name and Function Type Sym