T
B329
Canon 161 Calculator
Section: Modules - Gates & Display
Page: 4
Rendition: 2022 Feb 6
AND Gates
OR Gates
C
1.5n
Inverters
Buffers
R
5.6K
B221
D77
R
R
R
130K
R
12K
AND gate with controlled pull-up.
Used in marker decoders.
OR gate with controlled pull-down.
Used in marker decoders.
Distributed OR gate.
t
R
0
3.9K
1
4.7K
2
5.6K
bbAn-t
t
R
0
4.7K
1
5.6K
2
8.2K
4
33K
6
300K
7
330K
bbOn-t
RL
3K
T
B329
RB
51K
12K
1 t
V a r i a t i o n s
10
11
T=A538
12
T=B222
13
R=3K
14
R=3K T=B222
15
R=2K T=B222
16
R=2K B=221
17
R=5.6K to E
D77
R
2K
R
22
B77
N
bbcp
n1
n2
n4
n8
1
n2
n4
n8
n1
2
n4
1
2
n4
n1
n2
4
1
n2
4
n1
2
4
1
2
4
1
n1
2
n2
4
n4
8
n8
–2V
d-0
B77
N
bbcp
d-1
B77
N
bbcp
d-2
B77
N
bbcp
d-3
B77
N
bbcp
d-4
B77
N
bbcp
d-5
B77
N
bbcp
d-6
B77
N
bbcp
d-7
B77
N
bbcp
d-8
B77
N
bbcp
d-9
–V(L)
n1
8
1
8
d = digit (16 to 1)
bb = board (30,31,32,33,34)
c = connector (3,4)
p = pin (A to Z)
bbAdd0
-2
bbAdd1
-2
bbAdd2
-2
bbAdd3
-2
bbAdd4
-2
bbAdd5
-2
bbAdd6
-2
bbAdd7
-2
bbAdd8
-2
bbAdd9
-2
1
n1
2
n2
4
n4
8
n8
Display
n8
Display
8
n4 4
n2 2
n1 1
t
V a r i a t i o n s
0
C=none
1
2
C=none RL=1.8K
3
RL=1.8K
4
C=none RL=820
5
RL=820
6
C=none T=A538
7
C=1nF T=A538
8
C=none RL=1.8K T=A538
9
C=1nF RB=68K T=A538
0 t
V a r i a t i o n s
01
R=1K
N o t e s
• Gates are identified with a label of the form:
bbgn-t
where:
bb = board [30-40]
g = gate type (And,Or,inVerter,Buffer)
n = enumeration
t = type variation (see tables above)
• Logic 0 = 0V, GND, E
Logic 1 = –10V
bbBn-0t
bbVn-t
bbBn-1t
bbBn-D
bbAn-t
R
bbOn-t
R
bbOn-t
