Notes
• This CMU diagram is drawn in terms of normal CMOS positive logic levels, in contrast
to the negative levels of the 161. As such, there is an implicit logical inversion in the
connection between the calculator and the CMU.
CalcSig => nCmuSig
• Connector point NTL is unused on the calculator. It may be connected to –10V to
supply the CMU, alternatively a clip-lead from the CMU may be used to connect to
–10V.
• LED limiting resistors should be chosen appropriately for LEDs used.
• Alternatives to stop clock after keypress is registered:.
• CP => U4.10, U4.14 => U4.7. Stop after 8 clock cycles.
• OS => U4.10, U4.11 => U4.7. Stop on assertion of OS.
• Improvement: Add a Clock-Enabled LED driven by U6b.6.
• Bug: T-8 is derived from a ripple counter, glitches may stop the clock in the middle of
the digit, requiring two presses per digit.
Other Servicing Notes
• A & B Counters may be monitored with LEDs with 2K resistors connected between
the collector of the nQ transistors and –10V.
• The D Counter may be monitored by connecting 35B4 output (at 4.7K R near edge of
board 35) to –10V.
Revision Log
• 2001 Jan:
Version 1, original design and construction / bh.
• 2010 Nov:
Version 2, Digit and Interval controls added / bh.
• 2021 Dec:
Version 3, allow control over clocking when nFM / bh.
The Controller/Monitor Unit (CMU)
The 161 has an internal test connector which provides access to the master clock and most of the flag
registers. Presumably there was originally a service unit to plug into this connector. The CMU is a newly-
designed unit utilizing CMOS ICs. It provides monitors for the available flags along with manual control of the
master clock.
The 161 uses a direct-drive display (not multiplexed) and static memory technology, consequently the clock
can be slowed down or stopped without disrupting the display or state of the machine. The control aspect of the
CMU functions by inhibiting the normal delivery of clock pulses in the 161. Installing the CMU and flipping the
test-mode switch to the up position inserts a pulse transfer gate between the master clock of the 161 and the
rest of the calculator. The functioning of this gate is controlled by the keys of the CMU and the keys of the
calculator:
Calculator Keys:
The pressing of a calculator key enables clock pulses. This enables FK to
clock and pick up the keypress from OS.ST. Clocking is disabled when OS is
asserted.
Normal Calculator Mode (C): Enables normal delivery of clock pulses.
Repeat Mode (R):
Repeatedly allows one clock pulse through the gate at a rate determined by
the “Repeat Rate” control.
Stop / Clock Step (S):
Takes the CMU out of normal or repeat mode (stops continuous delivery of
clock pulses) and allows one clock pulse through the gate per press.
Digit Step (D):
Enables clock pulse delivery till the end of the next digit cycle. Typically this
will be 4 clock pulses, and will step the calculator thru one digit cycle.
Number Step (N):
Enables clock pulse delivery till the next end of a number cycle.
The pulse transfer gate is fully synchronised to the pulses from the master clock, permitting the mode to be
changed at any time, between or during, execution of operations.
Using the CMU
1. Begin with the 161 turned off.
2. Plug the CMU edge connector into the test connector of the 161.
3. If NTL has not been connected to –10V, connect the CMU power lead to the blue (-10V) power supply
connector.
4. Connect the KOR lead to N302B.
5. Flip the test-mode toggle switch of the 161 to the up position.
6. Turn the 161 on.
7. Press the “N” key of the CMU. The 161 should function normally.
When operating in other than normal mode, a key pressed on the 161 may need to be held down until the
operation is complete. This is necessary for some operations because the calculator logic utilises the state of the
keyboard during execution. The keyboard state is not fully latched at the beginning of an operation. Once the
state machine makes it to CC2 and beyond, the key may be released, an exception being the Total key must be
held down through CC7.
The Probe leads can be used to monitor other signals in the 161. The probes may not be valid for (and
probably should not be connected to) the output of OR gates due to the +10 bias on such outputs, as this may
pull a CMOS input below Vss of the IC.
Canon 161 Calculator
Section: CMU Operation
Page: CMU.2
Rendition: 2022 Feb 6
