Cameron KS21TK305A, Service Manual

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SERVICE MANUAL
24
sound decoder, RDS, ISP, acquisition, display, display RAM and digital video interface. The
software reset is executed by initially setting the corresponding bit to
‘
1
’
followed by clearing the bit
to
‘
0
’
. The reset is launched after the falling edge of this process. It takes approximately 200 ms to
complete the internal reset sequence. Please note that of course the micro controller, its peripherals
(e.g. timers) and the program flash are not affected by this reset.
1.6.2 Power Modes
1.6.2.1 Stand-by mode
During Stand-by mode, the Acquisition, Display, RDS, and SSD sections of the device are
disabled. The following functions remain active:
•
80c51 CPU Core
•
I2C
•
RCP (Remote Control Pre-processor)
•
Timer/Counters
•
WatchDog Timer
•
UART, SAD and PWMs
To enter Stand-by mode, the STANDBY bit in the ROMBANK register must be set. The status
of all SFRs, internal RAM contents are maintained, as are the device output pin values, but the
contents of Display memory are lost. Since the output values on RGB and VDS are maintained the
display output must be disabled before entering this mode. This mode should be used in conjunction
with both Idle and Power-Down modes.
It is not recommended to enter either the Idle mode or Power-Down mode directly from the
application mode. During Standby mode execution the necessary provisions are executed to safely
enter the subsequent modes and re-cover from them.
1.6.2.2 Idle mode
During Idle mode, Acquisition, Display, RDS, SSD and the CPU sections of the device are
disabled. The following functions remain active:
•
I2C
•
RCP
•
Timer/Counters
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