Chapter 4: Feature Description
Synchronization
IEEE-1588 Transparent Clock
PTP 820S supports and transport a PTP optimized message-based protocol that can be
implemented across packet-based networks. To ensure minimal packet delay variation (PDV), PTP
820S’s synchronization solution includes 1588v2-compliant Transparent Clock. Transparent Clock
provides the means to measure and adjust for delay variation, thereby ensuring low PDV.
Note
IEEE-1588 Transparent Clock is planned for future release.
PTP calculates path delay based on the assumption that packet delay is constant and that delays
are the same in each direction. Delay variation invalidates this assumption. High PDV in wireless
transport for synchronization over packet protocols, such as IEEE-1588, can dramatically affect the
quality of the recovered clock. Slow variations are the most harmful, since in most cases it is more
difficult for the receiver to average out such variations.
PDV can arise from both packet processing delay variation and radio link delay variation.
Packet processing delay variation can be caused by:
•
Queuing Delay – Delay associated with incoming and outgoing packet buffer queuing.
•
Head of Line Blocking – Occurs when a high priority frame, such as a frame that contains IEEE-
1588 information, is forced to wait until a lower-priority frame that has already started to be
transmitted completes its transmission.
•
Store and Forward – Used to determine where to send individual packets. Incoming packets
are stored in local memory while the MAC address table is searched and the packet’s cyclic
redundancy field is checked before the packet is sent out on the appropriate port. This process
introduces variations in the time latency of packet forwarding due to packet size, flow control,
MAC address table searches, and CRC calculations.
Radio link delay variation is caused by the effect of ACM, which enables dynamic modulation
changes to accommodate radio path fading, typically due to weather changes. Lowering
modulation reduces link capacity, causing traffic to accumulate in the buffers and producing
transmission delay.
Note
When bandwidth is reduced due to lowering of the ACM modulation point, it is
essential that high priority traffic carrying IEEE-1588 packets be given the highest
priority using PTP 820S’s enhanced QoS mechanism, so that this traffic is not
subjected to delays or discards.
These factors can combine to produce a minimum and maximum delay, as follows:
•
Minimum frame delay can occur when the link operates at a high modulation and no other
frame has started transmission when the IEEE-1588 frame is ready for transmission.
•
Maximum frame delay can occur when the link is operating at QPSK modulation and a large
(e.g., 1518 bytes) frame has just started transmission when the IEEE-1588 frame is ready for
transmission.
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