PRELIMINARY
Document type:
Title:
Revision date:
Revision:
User's Manual (MUT)
Mod. V1729 4 Channel 12 Bit Sampling ADC
22/06/2005
3
NPO:
Filename:
Number of pages:
Page:
00109/04:V1729.MUTx/03 V1729_REV3.DOC
38
4
LIST OF FIGURES
F
IG
. 1.1:
DATA FLOW IN THE BOARD
...................................................................................................................5
F
IG
. 2.1:
CHRONOGRAM OF THE STOPPING OF THE ACQUISITION
.........................................................................7
F
IG
. 2.2:
CENTERING OF THE
T
RIGGER IN THE ACQUISITION WINDOW FOR TWO
POSTTRIG
CASES
...................7
F
IG
. 2.3:
SIMPLIFIED DESCRIPTION OF THE TRIGGER SELECTION CHAIN
..............................................................9
F
IG
. 2.4:
SIMPLIFIED DESCRIPTION OF THE TRIGGER VALIDATION SYSTEM
........................................................10
F
IG
. 2.5:
BLOCK DIAGRAM OF A STANDARD ACQUISITION
................................................................................12
F
IG
. 2.6:
TWO POSSIBILITIES FOR DETECTION AND FOR TREATMENT OF THE REQUEST
......................................13
F
IG
. 2.7:
UNFOLDING OF THE CIRCULAR MEMORY
............................................................................................14
F
IG
. 3.1:
DIAGRAM OF THE CALIBRATION OF THE VERNIERS
.............................................................................18
F
IG
. 4.1: M
OD
. V1729 F
RONT
P
ANEL
..............................................................................................................22
F
IG
. 4.2:
IMPLEMENTATION OF THE CONNECTORS AND CONFIGURATION ELEMENTS ON THE
V1729.................23
F
IG
. 4.3:
SYNOPSIS OF THE
V1729
BOARD
........................................................................................................35
F
IG
. 4.4:
S
YNOPSIS OF AN ACQUISITION CHANNEL ON THE
MATACQ
BOARD
.................................................36