C-Max CMM-9304-V2.1, Manual, Page: 4 / 11

CMM-9304-V2.1
Bluetooth 4.2 / 5.0 compatible module
SPEC No.
CMM-9304-V2.1
BLE module
Revision
2.8
State
2017-11-13
C-MAX printed
2017-11-13
Version
English
Page
4 of 11
C-MAX
2. SPI Slave Interface
The CMM-9304 module has a Slave SPI to be used for the HCI (or ACI) transport layer.
2.1 SPI Slave Features
The SPI slave block supports following features:

4 wire SPI interface (SCK, CSN, MISO, MOSI) with flow control (RDY output signal).

Half duplex communication. Direction (write/read) is determined by a control byte

Supported SPI clock speed up to 16MHz.

Motorola compliant, clock polarity CPOL = 0 (clock is inactive low), clock phase CPHA = 0
(data is valid on clock rising edge).

All 4 SPI clock polarity/phase configurations.

64 bytes long RX FIFO for reception and 64 bytes long TX FIFO for transmission.

Multi byte transactions (without de-asserting CSN between bytes)
2.2 SPI Slave RDY signal
RDY signal has following meaning depending on SPI transaction phase:
1. Data ready (when CSN = '1')

RDY at '1'

SPI Slave has some data to send.

RDY at '0'

SPI Slave has no data to send.
2. SPI ready (between CSN falling edge and end of 1st header byte)
•
RDY at '1'

SPI Slave is ready and SPI transaction can start, SPI Master can transmit another
byte.
•
RDY at '0'

SPI Slave is not ready and SPI transaction cannot start. SPI master has to wait
until RDY is at '1'.
3. Buffer ready (between end of 1st header byte and CSN rising edge)
•
RDY at '1'

buffer is ready and byte can be written/read