Hardware Architecture
BCM5718 Programmer’s Guide
Broadcom
®
January 29, 2016 • 5718-PG108-R
Page 51
S e c t i o n 2 : H a r d w a r e A r c h i t e c t u r e
Theory of Operation
shows the major functional blocks and interfaces of the Ethernet controllers covered in this document.
Only a single port is illustrated in
. The dual-port controllers in this family of controllers essentially
replicate a second instance of the major areas of functionality shown in the diagram below. The dual-port
controllers have only a single PCIe and NVRAM interfaces.
There are two packet flows: MAC-transmit and receive. The device’s DMA engine bus-masters packets from
host memory to device local storage, and vice-versa. The host bus interface is compliant with PCIe standards.
The RX MAC moves packets from the integrated PHY into device internal memory. All incoming packets are
checked against a set of QOS rules and then categorized. When a packet is transmitted, the TX MAC moves
data from device internal memory to the PHY. Both flows operate independently of each other in full-duplex
mode. An on-chip RISC processor is provided for running value-added firmware that can be used for custom
frame processing. The on-chip RISC operates independently of all the architectural blocks; essentially, RISC is
available for the auxiliary processing of data streams.
Figure 1: Individual Port Functional Block Diagram
Receive
MAC
Rx
FIFO
Transmit
MAC
Tx
FIFO
Statistics
Rule
Check
Memory
Arbiter
Tx Frame Buffer
Memory
Send BD RING
RISC
Processor
Boot ROM
Frame Buffer
Manager
Queue
Memory
Read DMA
Read
FIFO
Write
DMA
Write
FIFO
Registers
PCIe Bus
Ring Controllers
Host Coalescing
Queue Management
Receive
GMII
Transmit
GMII
LED Control
PLL
LED Signals
125-MHz Clock
Receive BD RING
DMA Descriptor
Config
EEPROM Control
NVRAM
Interface
Physical Layer
Transceiver
PCIe
Rx Frame Buffer
Memory/RISC Scratch
Pad Memory
Applications
Processing
Engine
(APE runs
firmware such
as NC-SI)