BOSER Technology HS-1760, Manual, Page: 26 / 54

20
3.17 Watchdog Timer
Once the Enable cycle is active a Refresh cycle is requested before the
time-out period. This restarts counting of the WDT period. When the
time counting goes over the period preset of WDT, it will assume that
the program operation is abnormal. A reset system signal will restart
when such error happens.
The HS-1760 custom WDT circuit is implemented using the internal IO
of the Winbond Super I/O W83627UHG which is at 2Eh of LPC.
The following sample programs show how to enable, disable and
refresh the watchdog timer:
Sample Code
C Language for Watchdog Timer under DOS.
#include<stdio.h>
#include<dos.h>
static unsigned int 83627UHG_Port = 0x2e;
{
Outportb(83627UHG_Port,0x87);
Outportb(83627UHG_Port,0x87);
}
void W83627UHG_WDT(unsigned int count_setup)
{
unsigned int Counting, Register_Setup;
outportb(83627UHG_Port, 0x07);
outportb(83627U1, 8); // set as Logical
Device 8
if(count_value >= 60)
{
outportb(83627UHG_Port, 0xf5);
Register_Setup = inportb(83627U1);
Register_Setup |= 0x08;
outportb(83627U1, Register_Setup); /
/ set as minute mode
counting = count_setup / 60;
if((count_value%60) > 30)