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2.8 SPI
2.8.1 ECSPI
Full-duplex enhanced Synchronous Serial Interface, with data rate up to 52 Mbit/s. Configurable to support
Master/Slave modes, four chip selects to support multiple peripherals.
Signal
Description
Pin
Defaults Function
ECSPI1_SCLK
SPI1 Master clock put out;
169 UART3_RXD
ECSPI1_MISO
SPI1 Master data input; Slave data output
173 UART3_CTS
ECSPI1_MOSI
SPI1 Slave data input; Master data output
171 UART3_TXD
ECSPI1_SS0
SPI1 Chip Select0
175 UART3_RTS
ECSPI2_SCLK
SPI2 Master clock put out;
174 ECSPI2_SCLK
ECSPI2_MISO
SPI2 Master data input; Slave data output
172 ECSPI2_MISO
ECSPI2_MOSI
SPI2 Slave data input; Master data output
170 ECSPI2_MOSI
ECSPI2_SS0
SPI2 Chip Select0
176 ECSPI2_SS0
ECSPI3_SCLK
SPI3 Master clock put out;
156 UART1_RXD
ECSPI3_MISO
SPI3 Master data input; Slave data output
154 UART1_TXD
ECSPI3_MOSI
SPI3 Slave data input; Master data output
152 UART2_RXD
ECSPI3_SS0
SPI3 Chip Select0
150 UART2_TXD
2.8.2 QSPI
Signal
Description
Pin
Defaults Function
QSPIA_SCLK
SPIA Master clock put out;
Un-pinout QSPIA_SCLK for flash
QSPIA_SS0
SPIA Chip Select0
Un-pinout QSPIA_SS0 for flash
QSPIA_SS1
SPIA Chip Select1
Un-pinout SD3_STROBE for emmc
QSPIA_data0
SPIA data0
Un-pinout QSPIA_data0 for flash
QSPIA_ data1
SPIA data1
Un-pinout QSPIA_ data1 for flash
QSPIA_ data2
SPIA data2
Un-pinout QSPIA_ data2 for flash
QSPIA_ data3
SPIA data3
Un-pinout QSPIA_ data3 for flash
QSPIB_SCLK
SPIB Master clock put out;
Un-pinout SD3_DATA7 for emmc
QSPIB_SS0
SPIB Chip Select0
Un-pinout SD3_DATA5 for emmc
QSPIB_SS1
SPIB Chip Select1
Un-pinout SD3_DATA6 for emmc
QSPIB_data0
SPIB data0
Un-pinout SD3_DATA0 for emmc
QSPIB_ data1
SPIB data1
Un-pinout SD3_DATA1 for emmc
QSPIB_ data2
SPIB data2
Un-pinout SD3_DATA2 for emmc
QSPIB_ data3
SPIB data3
Un-pinout SD3_DATA3 for emmc
2.9 UART
Four Universal Asynchronous Receiver/Transmitter (UART) modules
Each of the UARTv2 modules supports the following serial data transmit/receive protocols and
