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Page 32

Appendix B

Page 32

01270146.doc

 Blue Chip Technology Ltd.

APPENDIX B - PC MAPS

PC XT/AT I/O Address Map

Address

Allocated to:

000-01F

DMA Controller 1 (8237A-5)

020-03F

Interrupt Controller 1 (8259A)

040-05F

Timer (8254)

060-06F

Keyboard Controller (8742) Control Port B

070-07F

RTC and CMOS RAM, NMI Mask (Write)

080-09F

DMA Page Register (Memory Mapper)

0A0-0BF

Interrupt Controller 2 (8259)

0F0

Clear NPX (80287) Busy

0F1

Reset NPX (80287)

0F8-0FF

Numeric Processor Extension (80287)

1F0-1F8

Hard Disk Drive Controller

200-207

Reserved

278-27F

Reserved for Parallel Printer Port 2

2F8-2FF

Reserved for Serial Port 2

300-31F

Reserved

360-36F

Reserved

378-37F

Parallel Printer Port 1

380-38F

Reserved for SDLC Communications, Bisync 2

3A0-3AF

Reserved for Bisync 1

3B0-3BF

Reserved

3C0-3CF

Reserved

3D0-3DF

Display Controller

3F0-3F7

Diskette Drive Controller

3F8-3FF

Serial Port 1

Summary of Contents for AOP-12D

Page 1: ...AOP 12D Multi Function Analogue Output Card User Manual...

Page 2: ......

Page 3: ...ical photocopied recorded or otherwise without the prior permission in writing from the publisher For permission in the UK contact Blue Chip Technology Information offered in this manual is correct at...

Page 4: ...nt Details 1 0 9 8 95 SH First approved issue new front sheet 2 0 20 12 95 EGW Addition of EMC information to Technical Section Errors corrected References to current outputs removed Added layout diag...

Page 5: ...8 Fitting the Card 8 USING THE CARD 9 External Input Output Connections 9 Analogue Connections 9 Analogue Voltage Outputs 10 Digital Connections 11 OPERATION OF THE CARD 12 Programmable Digital Input...

Page 6: ...ERING SYSTEMS 28 Binary and Hexadecimal Numbers 28 Base Address Selection 31 APPENDIX B PC MAPS 32 PC XT AT I O Address Map 32 PC XT Interrupt Map 33 PC AT Interrupt Map 34 DMA Channels 34 APPENDIX C...

Page 7: ...and outputs and analogue outputs There are 24 TTL compatible programmable digital input outputs available externally There are also three programmable timers One of the timer outputs is available ext...

Page 8: ...all O Ps Output Error Volts 0 5 of Span Output Settling Time 3 S to 1 LSB Data Transfer I O Port or DMA DMA Channels Supported 1 2 and 3 Fastest DMA Transfer Rate 12 S per Transfer Channel Selection...

Page 9: ...nput Outputs Number of Channels 24 Digital Inputs High Level Input 2 2 Volts minimum Current 10 A sink Low Level Input 0 8 Volts maximum Current 10 A source Digital Outputs Logic High Voltage 3 5 Volt...

Page 10: ...DMA transfer Timer 2 Uncommitted output available Timer 0 Resolution 1 S Minimum Time 2 S Maximum Time 130mS Timer 1 Resolution timer 0 output value Minimum Time 4 S Maximum Time 2 3 hours Timer 2 Res...

Page 11: ...complied with regarding earthing and the installation of boards The board must be installed with the backplate securely screwed to the chassis of the computer to ensure good metal to metal i e earth...

Page 12: ...end of the cable Failure to observe these recommendations may invalidate the EMC compliance Warning This is a Class A product In a domestic environment this product may cause radio interference in whi...

Page 13: ...is included in the Appendices Base Address Select an unused I O address range for the card The card requires a block of 16 contiguous addresses The base address is set on jumper block JP3 Fitting a li...

Page 14: ...setting of the DMA Acknowledge channels The settings must be the same on both JP2 and JP4 If DMA operation is not required the links may left open to allow the unused channels to be used by other card...

Page 15: ...lowing table shows the pin out of the D type analogue connector CON1 The pins are arranged in three rows PIN USAGE PIN USAGE PIN USAGE 1 V output 1 18 No connect 34 V output 12 2 No connect 19 V outpu...

Page 16: ...renced to these connections Measuring output voltages with reference to other ground points particularly the digital ground will give electrically noisy results The voltage output has a span from 10 V...

Page 17: ...5 15 DIO port B bit 6 16 DIO port B bit 7 17 DIO port C bit 0 18 DIO port C bit 1 19 DIO port C bit 2 20 DIO port C bit 3 21 DIO port C bit 4 22 DIO port C bit 5 23 DIO port C bit 6 24 DIO port C bit...

Page 18: ...appears to the PC as four ports The first three can be set as input or output by writing suitable codes to the fourth Control Port These four ports are mapped into the AOP 12d address map as follows...

Page 19: ...t 81 129 Output Output Output Input 82 130 Output Input Output Output 83 131 Output Input Output Input 88 136 Output Output Input Output 89 137 Output Output Input Input 8A 138 Output Input Input Outp...

Page 20: ...ing modes of the DAC these timers must be configured to run See the section on TIMER INITIALISATION for code examples to configure these timers The reference clock for timers 0 and 2 is 1Mhz Timer 1 i...

Page 21: ...s are mapped into the AOP 12d address map as follows BASE 8 Timer Counter 0 read write 9 Timer Counter 1 read write 10 Timer Counter 2 read write 11 Control register write only Bits 6 and 7 in the con...

Page 22: ...his writes 3 into the LOW 8 bits of the 16 bit counter register Output 0 to timer 0 count register base 8 This writes 0 into the HIGH 8 bits of the 16 bit counter register Output hex 78 to the timer c...

Page 23: ...ister to load the required value The low 8 bits are sent first followed by the high 4 bits Output Value Output Voltage 0 10 V 2048 0 V 4095 10 V The DAC section operates in one of two basic modes I O...

Page 24: ...e it is possible to output to all 12 channels by setting the AUTO CHANNEL SCANNING bit in channel enable register 2 When this bit is set after each DMA transfer the channel number will be incremented...

Page 25: ...R W Timer Timer 0 count register 9 R W Timer Timer 1 count register 10 R W Timer Timer 2 count register 11 R W Timer Timer control register DAC Control Register Base 0 DATA BIT FUNCTION 0 DAC Channel...

Page 26: ...t 1 0 Enable channel 2 output 1 Disable channel 2 output 2 0 Enable channel 3 output 1 Disable channel 3 output 3 0 Enable channel 4 output 1 Disable channel 4 output 4 0 Enable channel 5 output 1 Dis...

Page 27: ...tput 3 0 Enable channel 12 output 1 Disable channel 12 output 4 0 Disable AUTOMATIC channel scanning 1 1 Enable AUTOMATIC channel scanning 5 0 Enable DMA Cycle mode 2 1 Disable DMA Cycle mode 6 Not Us...

Page 28: ...amples EXAMPLE1 BAS EXAMPLE1 C These demonstrate the simple I O mode to output a single value to one analogue output channel EXAMPLE2 BAS EXAMPLE2 C These demonstrate reading and writing to the digita...

Page 29: ...port map Available positions are shown in the IBM PC Technical Reference Guide However for those who do not possess a copy of this document a good place is the location normally allocated to the prot...

Page 30: ...Ltd To set the base address to 300 Hex locate the jumper block JP3 labelled Base Address Set the following pattern on the links as indicated below with Connector CON2 on right hand side and the gold...

Page 31: ...Interrupts The DAC generates an interrupt signal at the end of a DMA transfer The interrupt is selected on jumper block JP1 The diagram below shows the DAC set to produce an interrupt request on IRQ3...

Page 32: ...ontrols which channel the DAC uses to request Direct Memory Access Only channels 1 2 and 3 are available Jumper JP2 sets the channel on which the DMA controller acknowledges the request It is essentia...

Page 33: ...Detailed Card Installation Page 27 Blue Chip Technology Ltd 01270146 doc Page 27 Card Layout Diagram KFA12o Card Layout showing Selector Link Positions...

Page 34: ...and HEXADECIMAL These two systems provide an alternative representation to decimal numbers For a binary number there are only 2 possible values 0 or 1 and as a result binary numbering is often known a...

Page 35: ...1 1 1 1 8 1 0 0 1 0 1 2 1 9 1 0 0 1 1 1 3 2 0 1 0 1 0 0 1 4 Notice how the next higher column does not increment until the lesser one to its right has overflowed Binary representation is ideally suit...

Page 36: ...forming a byte are divided into two groups of 4 bits known as NIBBLES With four bits there are 16 possible numeric combinations including zero A convenient method of representing each nibble is to use...

Page 37: ...rds cover a range of addresses usually 16 Decimal Therefore the low order four bits are not included but two higher order bits are added This gives an address range of 0 to 3F0 Hex The following diagr...

Page 38: ...Memory Mapper 0A0 0BF Interrupt Controller 2 8259 0F0 Clear NPX 80287 Busy 0F1 Reset NPX 80287 0F8 0FF Numeric Processor Extension 80287 1F0 1F8 Hard Disk Drive Controller 200 207 Reserved 278 27F Re...

Page 39: ...doc Page 33 PC XT Interrupt Map Number Allocated to NMI Parity 0 Timer 1 Keyboard 2 Reserved 3 Asynchronous Communications Secondary SDLC Communications 4 Asynchronous Communications Primary SDLC Comm...

Page 40: ...rd Output Buffer Full IRQ 2 Interrupt from CTLR 2 IRQ 8 Real time Clock Interrupt IRQ 9 S w Redirected to INT 0AH IRQ 2 IRQ 10 Reserved IRQ 11 Reserved IRQ 12 Reserved IRQ 13 Co processor IRQ 14 Fixed...

Page 41: ...L 8237 or compatible devices each containing four channels The first one is used for byte transfers in the bottom 1 MB of system memory the second can transfer words into the bottom 16 MB Blue Chip Te...

Page 42: ...A Channel 2 Current Address 0005H R W DMA Channel 2 Current Word Count 0006H R W DMA Channel 3 Current Address 0007H R W DMA Channel 3 Current Word Count 0008H R W Command Status Register 0009H R W DM...

Page 43: ...6 MODE Bit 0 5 AUTO INC DEC 4 AUTO INIT 3 TRANS MODE Bit 1 2 TRANS MODE Bit 0 1 CHAN SEL Bit 1 0 CHAN SEL Bit 0 Mode Bits Bit1 Bit 0 FUNCTION 0 0 Demand Mode 0 1 Single Mode 1 0 Block Mode 1 1 Not Us...

Page 44: ...NALOGUE OUT boards for outputting continuous wave forms Transfer Mode Bit 1 Bit 0 FUNCTION 0 0 Verify Transfer 0 1 Write Transfer 1 0 Read Transfer 1 1 Not Used Use WRITE TRANSFER if the I O board is...

Page 45: ...a mask bit for a particular channel disables the DMA operation on that channel Status Register Port 0BH READ 7 CHAN 3 DMA RQ 6 CHAN 2 DMA RQ 5 CHAN 1 DMA RQ 4 CHAN 0 DMA RQ 3 CHAN 3 at TC 2 CHAN 2 at...

Page 46: ...e physical memory address of the DMA transfer Addressing In order for DMA to operate correctly the page register and start address register should be set up to inform the DMA controller where in memor...

Page 47: ...VARPTR dat In this example the variables seg and offs would contain the SEGMENT and OFFSET addresses of the array dat In order to pass this address to the DMA controller the segment and offset values...

Page 48: ...e START address register for the DMA channel being used Load the length count into the TRANSFER LENGTH register Note that the DMA controller only transfers 8 bits at a time each value written to an AN...

Page 49: ...2060 OFFSET seg 2070 OFFSET OFFSET 16 2080 OFFSET OFFSET offs 2090 OFFSET OFFSET AND 65535 2100 REM Setup the DMA registers 2105 OUT HA 7 REM DISABLE DMA CHANNEL 3 2110 OUT HC 0 REM RESET BYTE SELECT...

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