12
SHM-768K
Timing Generator
This circuit supplies the transmit clock to the encoder. The setting of the
XMT CLK jumper selects one of three available clock sources:
• INTERNAL CLK (from the modem’s internal crystal oscillator)
• EXTERNAL CLK (from DTE)
• RECEIVE CLK (recovered from receive signal)
XMT Level
The XMT LEVEL jumper selects XMT level (0 or -6 dBm).
2.3.2 R
ECEIVER
Equalizer and Automatic Gain Control (AGC)
The equalizer and AGC circuitry are activated according to the baud rate and
automatically compensate for line attenuation.
CDP Decoder
The decoder demodulates the incoming CDP signal to NRZ.
Clock Recovery and Carrier Detect
The clock-recovery and carrier-detect circuits provide a received clock
synchronized with the data, and a carrier detect using a digital technique.
2.3.3 V.54 D
IAGNOSTICS
V.54 loops are activated manually from the front panel push-buttons, by Pins
18 and 21 of the RS-530, or Pin “h” or “j” of the V.35 interface. These pins can
be enabled or disabled separately by the DTE command jumpers (ALB and
RLB).
When using the SHM-768K as a tail-end to a digital network or multiplexor,
set the V.54 DELAY jumper (in the modems located close to the digital
network) to ON to prevent multiple loopbacks upon activation of RLB. The
delay jumper prevents the digital modems at the remote network side from
receiving the complete V.54 data sequence and, in turn, being induced into a
loop.
