Bimatek D 1045 VNP, Maintenance Manual

Page: 12 / 38

12
Decode board elements diagram 1
MEMWR-
VR_SEL
SPDIF
DUPRD0
R
A
M
A
D
D
7
MEMDA11
R200 0R
R
1
6
4
3
9
2
R
/1
%
R
A
M
A
D
D
6
R
A
M
D
A
T
6
R10 33
FB26 FBR
JP24
CN2.54MM2X2-M
3
4 1
2
BC6
0.1uF
R
A
M
A
D
D
1
0
R
A
M
D
A
T
1
1
R
A
M
D
A
T
3
MEMAD11
BC17
0.1uF
BC241 10nF
DSPVCC18
MEMAD15
RD40
10K (NC)
DSPVCC33
DSPVCC33
DEFECT
T
R
A
C
K
_
D
A
C
VSYNC
DUPTD0
MEMAD10
R
A
M
D
A
T
9
+
C16
100uF/16V
R
A
M
A
D
D
2
R
A
M
D
Q
M
R
A
M
D
Q
M
OSCOUT
+
C15
100uF/16V
TP7
1
.
R6 33
BC4
0.1uF
FS2
R
A
M
A
D
D
5
MEMAD[20:0]
DRVSB
A
A
F
_
T
E
R
A
M
C
S
0
-
R
A
M
A
D
D
1
0
MEMCS1-
MEMDA3
PLLCFGP
MEMDA0
INSW
MEMDA10
MEMAD1
BC10
0.1uF
BC243 10nF
+ C128
47uF/16V
BC27
0.1uF
DUPTD0
C105
330P
BC242 10nF
C225 22pF
TP511 1
.
BC21
0.1uF
Y_R_V
INSW
R
A
M
D
A
T
3
R
A
M
B
A
DSPVCC33
ALRCLK
R15
4.7K
OSCOUT
P
C
L
K
MEMDA12
R190 330R
BC28
0.1uF
R
A
M
A
D
D
7
R
A
M
D
A
T
9
12CCLK
L
IN
K
N
N
N
R
A
M
D
A
T
9
R
A
M
W
E
-
R22 4.7K
R125 10K
**
220pF
DSPVCC18
C224 22pF
IALRCLK
BC3
0.1uF
DSPVCC33
I2CDAT
R
A
M
D
A
T
2
R
A
M
A
D
D
8
R
A
M
D
A
T
0
R
A
M
A
D
D
9
BC12
0.1uF
D14
RLS4148 (NC)
FPC_STB
R
A
M
D
A
T
1
4
R
A
M
D
A
T
1
2
R
A
M
B
A
FPC_STB
AFEGND
AOUT2
AIN
MEMAD19
ICETCK
MEMDA5
R183
100K
R
A
M
D
A
T
1
AOUT1
R
A
M
A
D
D
2
R
A
M
A
D
D
1
0
R
A
M
B
A
BC19
0.1uF
R
F
A
_
S
D
A
T
A
CLOSE
DUPRD1
R
A
M
D
A
T
1
4
MEMDA9
MEMAD13
MEMAD8
R
A
M
A
D
D
3
BC9
0.1uF
R
A
M
D
A
T
1
5
SPDIF
RD39 10K (NC)
R
A
M
D
A
T
1
5
DRVSB
MEMWR-
HOMESW
DSPVCC33
ICETMS
R14
4.7K
BC7
0.1uF
D+5V
MEMCS1-
DUPTD1
AMUTE
MEMCS0-
R
A
M
R
A
S
-
MEMAD4
AOUT2
Q11
SST3904 1
2
3
R
A
M
D
A
T
1
2
BC25
0.1uF
R127
0R
S
P
IN
D
L
E
_
P
W
M
R
A
M
D
A
T
2
TP22
1
.
SPDL_SENS
/AUDIO_RESET
R
A
M
D
A
T
7
OUTSW
R
A
M
D
A
T
1
2
R
A
M
R
A
S
-
R
A
M
D
Q
M
R
A
M
A
D
D
0
DUPRD1
GPAIO
HSYNC
MEMCS0-
CLOSE
A
A
F
_
P
I
R
A
M
D
A
T
5
R
A
M
C
A
S
-
RN3 33R X4
1 2
3 4
5 6
7 8
I2CCLK
R
A
M
D
Q
M
R
A
M
D
A
T
6
Y2 27.000MHz
VGND
R
A
M
A
D
D
0
FB4 FBR
P L A Y M O D E : A L L O P E N
C104
330P
BC1
0.1uF
BC14
0.1uF
DSPVCC33
MEMAD12
C_B_U
ABCLK
OUTSW
R
A
M
D
A
T
7
R
A
M
D
Q
M
R
A
M
A
D
D
5
R
A
M
D
A
T
3
R
A
M
D
A
T
1
MEMAD20
IABCLK
R239 150
STANDBY
MIRR
P
C
L
K
R
A
M
D
A
T
4
LDON
A
A
F
_
C
E
R
A
M
D
A
T
6
ICETDO
R161 33
FB2 FBR
U15
ZR36768
12
1
2
3
4
5
6
7
8
9
10
11
50
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
51
52
5
3
5
4
5
5
6
2
5
6
5
7
5
8
5
9
6
0
6
1
7
2
6
3
6
4
6
5
6
6
6
7
6
8
6
9
7
0
7
1
8
3
7
3
7
4
7
5
7
6
7
7
7
8
7
9
8
0
8
1
8
2
9
1
8
4
8
5
8
6
8
7
8
8
8
9
9
0
1
0
1
9
2
9
3
9
4
9
5
9
6
9
7
9
8
9
9
1
0
0
1
0
2
1
0
3
1
0
4
105
156
155
154
152
151
145
136
144
143
142
141
140
139
138
127
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
2
0
5
2
0
4
2
0
2
1
9
2
1
9
0
2
0
0
1
8
7
1
9
5
1
9
7
1
8
6
1
8
5
1
8
4
1
7
5
1
7
4
1
7
3
1
7
2
1
7
1
1
5
7
1
6
9
1
6
0
1
6
7
1
6
5
1
6
4
1
6
3
1
6
2
1
6
1
1
5
9
1
5
8
39
40
41
42
43
44
45
46
47
48
49
106
107
108
109
126
128
129
130
131
132
133
134
135
137
146
147
148
149
150
153
1
6
6
1
6
8
1
7
0
1
8
3
1
8
2
1
8
1
1
8
0
1
7
9
1
7
8
1
7
7
1
7
6
1
8
8
1
8
9
1
9
1
1
9
3
1
9
4
1
9
6
1
9
8
1
9
9
2
0
1
2
0
3
2
0
6
2
0
7
2
0
8
GNDP
SSCRXD/GPCIO[17]
MEMCS[1]#/GPCIO[18]
VDDP
MEMAD[15]/PLLPROG[0]
MEMAD[16]/PLLPROG[1]
MEMAD[14]/PLLPROG[2]
MEMAD[13]/AFETESTEN
MEMAD[12]/[PLLCFGA]
MEMDA[15]
MEMAD[11]/[PLLCFGP]
MEMDA[7]
GNDP
MEMAD[10]/[TESTMODE]
MEMDA[14]
MEMAD[9]
MEMDA[6]
MEMAD[8]
MEMDA[13]
MEMDA[5]
MEMAD[20]/[GPCIO19]/[MEMCS#2]
VDDP
MEMDA[12]
MEMWR#
MEMDA[4]
VDDC
MEMDA[11]
MEMDA[3]
MEMAD[19]/[PLLSEL]
GNDC
MEMDA[10]
MEMAD[18]
GNDP
MEMDA[2]
MEMAD[17]
MEMDA[9]
MEMAD[7]
MEMDA[1]
MEMAD[6]
VDD-IP
VDDP
R
A
M
A
D
D
[4
]
R
A
M
A
D
D
[3
]
R
A
M
A
D
D
[5
]
G
N
D
P
R
A
M
A
D
D
[2
]
R
A
M
A
D
D
[6
]
V
D
D
P
R
A
M
A
D
D
[1
]
R
A
M
A
D
D
[7
]
R
A
M
A
D
D
[0
]
G
N
D
P
R
A
M
A
D
D
[8
]
V
D
D
C
R
A
M
A
D
D
[1
0
]
G
N
D
C
R
A
M
A
D
D
[9
]
V
D
D
P
R
A
M
A
D
D
[1
1
]
R
A
M
C
S
[0
]#
/R
A
M
B
A
[1
]
R
A
M
B
A
[0
]
G
N
D
P
R
A
M
C
S
[1
]#
R
A
M
R
A
S
#
R
A
M
C
A
S
#
V
D
D
P
R
A
M
W
E
#
R
A
M
D
Q
M
G
N
D
P
C
L
K
P
C
L
K
V
D
D
P
C
L
K
R
A
M
D
A
T
[8
]
G
N
D
P
R
A
M
D
A
T
[7
]
R
A
M
D
A
T
[9
]
R
A
M
D
A
T
[6
]
V
D
D
P
R
A
M
D
A
T
[1
0
]
R
A
M
D
A
T
[5
]
R
A
M
D
A
T
[1
1
]
G
N
D
P
R
A
M
D
A
T
[4
]
V
D
D
C
R
A
M
D
A
T
[1
2
]
G
N
D
C
R
A
M
D
A
T
[3
]
V
D
D
P
R
A
M
D
A
T
[1
3
]
R
A
M
D
A
T
[2
]
R
A
M
D
A
T
[1
4
]
R
A
M
D
A
T
[1
]
R
A
M
D
A
T
[1
5
]
R
A
M
D
A
T
[0
]
VDDP
DUPTD1/GPCIO38
DUPRD1/GPCIO37
VDD-IP
DUPRD0/GPCIO35
GNDP
GPCI/O[32]
GPCI/O[31]
VDDP
GCLKA
GCLKP
XO
VDDA
RESET#
GNDA
VDDP
GNDP
HSYNC/GPCIO25/[CJTDO]
VDDC
VSYNC/GPCIO24/[CJTDI]
GNDC
AIN/[GPCIO23/CJTCK]
VDDP-A2
AMCLK
GNDP-A2
ABCLK
ALRCLK
GPAIO/[AOUT3]
AOUT[0]
AOUT[1]/[GPCIO22]
AOUT[2]/[GPCIO21]
SPDIF
S
L
E
D
P
U
L
S
E
/I
D
G
P
C
IO
6
V
D
D
P
G
N
D
P
V
D
D
C
G
N
D
C
D
E
F
E
C
T
/I
D
G
P
C
IO
5
P
W
M
A
C
T
[0
]/
G
P
C
IO
3
9
G
N
D
P
W
M
V
D
D
P
W
M
G
N
D
A
F
E
S
V
B
IA
S
S
1
V
B
IA
S
S
0
V
D
D
A
F
E
S
G
N
D
A
F
E
R
F
R
F
IN
N
R
F
IN
P
V
D
D
A
F
E
R
F
G
N
D
D
A
C
D
D
A
C
D
R
IV
E
[1
]
V
D
D
D
A
C
D
A
C
D
R
IV
E
[0
]
G
N
D
D
A
C
B
S
2
G
N
D
D
A
C
P
R
S
E
T
C
/B
/U
Y
/R
/V
/[
C
]
C
V
B
S
/C
/[
Y
]
C
V
B
S
/G
/Y
MEMDA[8]
MEMAD[5]
VDDP
MEMDA[0]
MEMAD[4]
MEMRD#
MEMAD[3]
MEMAD[2]
MEMCS[0]#
MEMAD[1]/[BOOTSEL2]
MEMAD[0]/[A]PLLSEL/[BOOTSEL1]
CPUNMI/GPCIO[20]
GNDP
[A]GPCIO110/BOOTSEL1/[AOUT3/ICGPCIO0]
[A]GPCIO111/BOOTSEL2/[IDGPCIO0]
COSYNC/GPCIO120/[ICGPCIO1/CJTMS]
GPCIO26/ICETMS/[DJTMS]
ICETDI/GPCIO122/[ICGPCIO2/DJTDI]
ICETDO/GPCIO123/[IDGPCIO1/DJTDO]
ICETCK/GPCIO27/[DJTCK]
GPCIO28/DJTMS
GPCIO29/DJTDI
GPCIO30/DJTDO
GPCIO128/DJTCK/[ICGPCIO3]
GPCI/O[130]/[IDGPCIO2]
GPCI/O[135]/[ICGPCIO4]
GPCI/O[33]
GPCI/O[137]/[ICGPCIO5]
GPCI/O[34]
GPCI/O[139]/[IDGPCIO3]
DUPTD0/GPCIO36
G
N
D
D
A
C
P
S
V
D
D
D
A
C
S
G
N
D
D
A
C
D
S
A
D
C
IN
0
A
D
C
IN
1
A
D
C
IN
2
A
D
C
IN
3
A
D
C
IN
4
A
D
C
IN
5
A
D
C
IN
6
A
D
C
IN
7
P
W
M
A
C
T
[1
]/
G
P
C
IO
4
0
P
W
M
C
O
[0
]/
G
P
C
IO
4
1
P
W
M
C
O
[1
]/
G
P
C
IO
4
2
P
W
M
C
O
[2
]/
G
P
C
IO
4
3
P
W
M
C
O
[3
]/
G
P
C
IO
4
4
P
W
M
C
O
[4
]/
G
P
C
IO
4
5
P
W
M
C
O
[5
]/
G
P
C
IO
4
6
P
W
M
C
O
[6
]/
G
P
C
IO
1
5
2
/[
ID
G
P
C
IO
4
]
IC
G
P
C
IO
6
G
P
C
IO
1
5
9
/[
IC
G
P
C
IO
7
]
S
P
IN
D
L
E
D
P
U
L
S
E
/I
D
G
P
C
IO
7
S
S
C
C
L
K
/G
P
C
IO
4
7
S
S
C
T
X
D
/G
P
C
IO
1
6
PLLCFGA OPEN
R
2
2
7
4
.7
K
R162 33
JP23
1
2
OSCIN
R
A
M
C
S
1
-
R
A
M
A
D
D
9
DUPTD1
R
A
M
D
A
T
1
3
CJTDO
R228 33
IRRCV
12CDAT
R
A
M
A
D
D
1
MEMDA6
U1
K4S161622C-TC/L70
1 2 3 4 5 6 7 8 9 1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
V
D
D
D
Q
0
D
Q
1
V
S
S
Q
D
Q
2
D
Q
3
V
D
D
Q
D
Q
4
D
Q
5
V
S
S
Q
D
Q
6
D
Q
7
V
D
D
Q
L
D
Q
M
W
E
C
A
S
R
A
S
C
S
B
A
A
1
0
/A
P
A
0
A
1
A
2
A
3
V
D
D
V
S
S
D
Q
1
5
D
Q
1
4
V
S
S
Q
D
Q
1
3
D
Q
1
2
V
D
D
Q
D
Q
1
1
D
Q
1
0
V
S
S
Q
D
Q
9
D
Q
8
V
D
D
Q
N
C
U
D
Q
M
C
L
K
C
K
E
N
C
A
9
A
8
A
7
A
6
A
5
A
4
V
S
S
AOUT1
**
2.7uH
BC46
15P(NC)
+3.3V
R
A
M
D
A
T
1
1
R
A
M
A
D
D
3
IAMCLK
RF33V
R
F
A
_
S
D
E
N
MEMAD2
BC33
0.1uF
TP3
1
. R
F
IN
P
M
N
T
R
MEMAD5
MEMAD17
R12
4.7k
R126 5.1K
D O W N L O A D M O D E : S H O R T 1 - 3 & 2 - 4
P
C
L
K
R
A
M
R
A
S
-
BC18
0.1uF BC24
0.1uF
R
A
M
A
D
D
4
R
2
5
0
7
5
C100
0.1uF
FPC_DOUT
CVBS_G_Y
STANDBY
BC13
0.1uF
D+5V
RESET-
R
A
M
D
A
T
8
BC2
0.1uF
R
A
M
C
A
S
-
R
A
M
A
D
D
4
VGND
R
A
M
D
A
T
1
R
A
M
D
A
T
0
R79 0
not install
S
L
E
D
_
P
W
M
/AUDIO_RESET
AIN
MEMDA13
BC15
0.1uF
R
A
M
A
D
D
2
LDON
R
A
M
A
D
D
1
R
A
M
D
A
T
5
BC26
0.1uF
+ C127
47uF/16V
R
A
M
C
S
0
-
ICETDI
BC20
0.1uF
Q12
SST3904 1
2
3
U3
K4S161622C-TC/L70
1 2 3 4 5 6 7 8 9 1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
V
D
D
D
Q
0
D
Q
1
V
S
S
Q
D
Q
2
D
Q
3
V
D
D
Q
D
Q
4
D
Q
5
V
S
S
Q
D
Q
6
D
Q
7
V
D
D
Q
L
D
Q
M
W
E
C
A
S
R
A
S
C
S
B
A
A
1
0
/A
P
A
0
A
1
A
2
A
3
V
D
D
V
S
S
D
Q
1
5
D
Q
1
4
V
S
S
Q
D
Q
1
3
D
Q
1
2
V
D
D
Q
D
Q
1
1
D
Q
1
0
V
S
S
Q
D
Q
9
D
Q
8
V
D
D
Q
N
C
U
D
Q
M
C
L
K
C
K
E
N
C
A
9
A
8
A
7
A
6
A
5
A
4
V
S
S
MEMRD-
OPEN
V
R
R
A
M
A
D
D
4
IRRCV
R
A
M
A
D
D
9
R
A
M
D
A
T
4
MEMDA1
FB3
FBR
CJTCK
R
A
M
A
D
D
6
BC11
0.1uF
SDRAM speed <=7ns
F
O
C
U
S
_
D
A
C
AMCLK
DUPRD0
R
A
M
D
A
T
1
4
T
P
1
1
.
JP22
CN2.54MM2P-M(NMI button)
1 2
DEFECT
R
A
M
D
A
T
5
CJTDI
R
A
M
D
A
T
7
R20
4.7k
RESET-
MEMAD9
MEMAD0
C101
0.22uF (NC)
MEMDA15
R
A
M
A
D
D
0
R
A
M
D
A
T
1
5
MEMAD14
+ C17
100uF/16V
HOMESW
A
A
F
_
F
E
DEM
OSCIN
R
A
M
A
D
D
1
MEMDA7
R
A
M
D
A
T
1
0
BC45
15P(NC)
R
A
M
D
A
T
4
R
A
M
D
A
T
2
MEMDA2
R
A
M
C
S
1
-
GND
SGND
MIRR
R
A
M
D
A
T
1
0
R
A
M
D
A
T
1
1
AOUT0
MIC_DET
R
A
M
A
D
D
6
R
A
M
D
A
T
8
BC30
0.1uF
MEMDA14
MEMAD3
R
A
M
D
A
T
1
3
IP
C
L
K
MEMRD-
DSPVCC33
MEMDA[15:0]
V
R
1
R
A
M
A
D
D
7
R
F
IN
N
HSYNC
DSPVCC18
RESET-
BC8
0.1uF
R
A
M
D
A
T
8
R
A
M
A
D
D
3
MEMAD6
+
C14
100uF/16V
CVBS_C
VSYNC
R
A
M
C
A
S
-
MEMAD16
MEMAD18
FPC_CLK
FPC_CLK
D
S
P
V
C
C
3
3
R9 33
C24
10u/16V (NC)
TP4
1
.
+ C4
47uF/16V
R
A
M
W
E
-
MEMDA8
FPC_DOUT
R
A
M
A
D
D
8
R
A
M
D
A
T
1
0
R
A
M
W
E
-
R
F
A
_
S
C
L
K
FS1
AOUT0
R
A
M
A
D
D
5
MEMDA4
R234 33
R19
2k
R
A
M
A
D
D
8
R
A
M
D
A
T
1
3
R
A
M
D
A
T
0
CJTMS
MEMAD7
BC5
0.1uF
BC29
0.1uF
U s e p i n 1 2 8 # , 1 3 0 # , 1 3 1 # o f I 6 4 t o o u t p u t A M U T E
F S 2 a n d D E M c o n t r o L s i g n a l .
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