Operation Manual
EL320.240.36-HB Display
Beneq Oy
Olarinluoma 9
Tel. +358 9 7599 530
VAT ID FI19563372
FI-02200 Espoo
Fax +358 9 7599 5310
www.beneq.com
Finland
www.lumineq.com
Date: February 13, 2017
Document number: ED000812C
Page | 8
3.4
Interface information
Beneq TFEL Small Graphics Displays (SGD) incorporate an interface that is similar to many
LCD interfaces. This interface is supported by a variety of off-the-shelf chip sets, which take
care of all the display control functionality, freeing the system processor for other tasks.
Designers should select the chip set that best suits their particular architecture and price
point.
3.4.1
Video input signals
The end of the top line of a frame is marked by VS, vertical sync, signal as shown in Figure 2.
The end of each row of data is marked by HS. A continuous low state of the VS input signal of
1.2 seconds will shut the display scan.
3
4
5
6
7
8
9
1
2
10
11
Second Line
VID Data
First Line
VID Data
Pixels: a b c d
Pixels: w x y z
HS
VID 0-3
VCLK
HS
VS
Vertical Timing
Horizontal Timing
Figure 2. Video input timing diagram
Timing is compatible with LCD graphics controllers such as the S1D13700 or RA8835.
