Benefon SPICA TDP-60-HN, Service Manual, Page: 43 / 128

1.3.1999
4A1900GB.fm 5
Product: TDP-60-HN / OA1900 Processor/Audio
5.1.2.6 Circuit Diagram
The processor and audio circuits diagram is split into four parts. Signals in the
circuit diagrams have been given names, and signals with the same name are
connected between diagrams (<x> = page).
5.1.3 Functions
5.1.3.1 µCBIC
I302 is itself a processor-asic circuit. It is comprised H8/300H-cpu, 10k*8
CMOS RAM, 8 A/D, 4 D/A, 48 pcs I/O lines, 3 series-interfaces, 2 modem-
interfaces, i2c-interface, frequency counter, realtime clock, timers and 4, 8
MHz clock oscillator. The µCBIC divides this by 4 to get timing signal E.
When the processor is operating, RESET = VCC, VCC = 3.3V, E = 1,2MHz.
5.1.3.2 Memories
Memory and external I/O-circuit address coding is done with the µCBIC circuit
I302. The circuit options CE, OE and WE are 0-active.
The program memory is in 512k*8 EPROM. The program uses the addresses
2100H 3E8000H.
RAM-memory is 10k*8 CMOS RAM and included to the µCBIC. µCBIC use
own power supply voltage whitch is VRAM and that is always operating, even
when the radio is in the OFF state.
5.1.3.3 The Modem
The FFSK modem is located in the audio circuit. The modem is connected to
the µCBIC by a series line, input to synchronised port, and transmission is
13 VCC power supply voltage 3.3V
14 DAO L:control data H:display data 0/VCC
15...17 VCC power supply voltage 3.3V
18...23 nc not connected
24 DSCL serial clock line for data 0/VCC
25 DSI serial data input
26 GND ground
27...34 connected to the voltage components
35 VCC power supply voltage 3.3V
36...40 connected to the voltage components
41 nc not connected
Page 1 of 5 module connector pins
2 of 5 power display
3 of 5 µCBIC, EPROM, SIS-function
4 of 5 audio parts