Beckhoff KL5101, Documentation, Page: 33 / 40

Access from the user program
KL5101 33 Version: 3.1
Status byte for process data exchange
The status byte is transmitted from the terminal to the controller. The status byte contains various status bits
of the KL5101.
Bit 7 6 5 4 3 2 1 0
Name REG=0 - State_Input Overflow Underflow CntSet_Acc Latch_Ext_Val/
RD_Period_Q
Latch_Val
Bit Name
5 State_Input
The state of the Status input is mapped in this Bit (adjustable via feature register [
}
30] ).
4 Overflow This bit is set if an overflow (65535 to 0) of the 16-bit counter occurs.
It is reset when the counter exceeds a third of the measuring range (21845 to 21846) or as soon as an un-
derflow occurs.
3 Underflow This bit is set if an underflow (0 to 65535) of the 16-bit counter occurs.
It is reset when the counter drops below two thirds of the measuring range (from 43690 to 43689), or imme-
diately an overflow occurs.
2 CntSet_Acc The data for setting the counter has been accepted by the terminal.
1 Latch_Ext_Val An external latch pulse has occurred. The data D2, D3 in the process image correspond to the latched
value when the bit is set. To reactivate the latch input, En_Latch_Ext must first be removed and then set
again.
RD_Period_Q Data bytes 2, 3 and 4 contain the period duration.
0 Latch_Val A zero point latch has occurred. The data D2, D3 in the process image correspond to the latched value
when the bit is set. To reactivate the latch input, En_Latch must first be removed and then set again.
5.5.2 Register communication
Register access via process data exchange
• Bit 7=1: Register mode
If bit 7 of the control byte is set, the first two bytes of the user data are not used for process data
exchange but written into the register set of the terminal or read from it.
• Bit 6=0: read, bit 6=1: write
Bit 6 of the control bytes is used to specify whether a register should be read or written.
◦ Bit 6=0: A register is read without changing it. The value can be found in the input process image.
◦ Bit 6=1: The user data are written into a register. The process is complete once the status byte in
the input process image has returned an acknowledgment (see example).
• Bit 0 to 5: Address
The address of the register to be addressed is entered in bits 0 to 5 of the control byte
Control byte in register mode (REG=1)
Bit 7 6 5 4 3 2 1 0
Name REG=1 W/R A5 A4 A3 A2 A1 A0
REG = 0
bin
: Process data exchange
REG = 1
bin
: Access to register structure
W/R = 0
bin
: Read register
W/R = 1
bin
: Write register
A5..A0 = register address
Addresses A5...A0 can be used to address a total of 64 registers.