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3-6 Advanced Chipset Features
The Advanced Chipset Features Setup option is used to change the values of the chipset
registers. These registers control most of the system options in the computer.
Phoenix – AwardBIOS CMOS Setup Utility
Advanced Chipset Features
Item Help
DRAM Timing Selectable [By SPD]
x CAS Latency Time [2]
x Active to Precharge Delay [6]
x DRAM RAS# to CAS# Delay [3]
x DRAM RAS# Precharge [3]
DRAM Data Integrity Mode [Non- ECC]
MGM Core Frequency [Auto Max 266MHz]
System BIOS Cacheable [Enabled]
Video BIOS Cacheable [Disabled]
Memory Hole At 15M-16M [Disable]
Delay Transaction [Enabled]
Delay Prior to Thermal [16 Min]
AGP Aperture Size <MB> [64]
** On-Chip VGA Setting **
On-Chip VGA [Enable]
On-Chip Frame Buffer Size [32MB]
Boot Display [CRT]
Panel Number [1]
Menu Level >
↑↓→←
Move Enter:/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Optimized Defaults F7:Standard Defaults
DRAM Timing Selectable
When “By SPD” has been select, BIOS will read SDRAM module SPD information pre-
define by memory module manufacture or use manually defined settings.
CAS Latency Time
When synchronous DRAM is installed, the number of clock cycles of CAS latency
depends on the DRAM timing. The settings are: 2T and 2.5T.
Note: Change these settings only if you are familiar with the chipset.
Active to Precharge Delay
Fast
gives faster performance; and
Slow
gives more stable performance. This field
applies only when synchronous DRAM is installed in the system. The settings are: 5T,
6T and 7T.
