BBK BBK921D, Service Manual

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4 Banks x 1M x 16Bit Synchronous DRAM
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.4/Nov.00
DESCRIPTION
The Hyundai HY57V651620B is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the Mobile applica-
tions which require low power consumption and extended temperature range. HY57V651620B is organized as 4banks
of 1,048,576x16.
HY57V651620B is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and out-
puts are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very
high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or Full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined
design is not restricted by a `2N` rule.)
FEATURES
• Single 3.3V
±
10% power supply
• All device pins are compatible with LVTTL interface
• JEDEC standard 400mil 54pin TSOP-II with 0.8mm
of pin pitch
• All inputs and outputs referenced to positive edge of
system clock
• Data mask function by UDQM or LDQM
• Internal four banks operation
• Auto refresh and self refresh
• 4096 refresh cycles / 64ms
• Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
• Programmable CAS Latency ; 2, 3 Clocks
ORDERING INFORMATION
Part No. Clock Frequency Power Organization Interface Package
HY57V651620BTC-7I 143MHz
Normal
power
4Banks x 1Mbits
x16
LVTTL 400mil 54pin TSOP II
HY57V651620BTC-75I 133MHz
HY57V651620BTC-10SI 100MHz
HY57V651620BLTC-7I 143MHz
Lower
Power
HY57V651620BLTC-75I 133MHz
HY57V651620BLTC-10SI 100Mhz
IC BLOCK DIAGRAM & DESCRIPTION
IC U206 SDRAM-HY57V65162B
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