BARRETT 900 SERIES TRANSCEIVERS
Mute attack timing is controlled by C191 and R121. Release timing is set by
C191 and R122 and
microprocessor introduced delays.
The signal PWR ADJ from the DAC U38 via buffer U10B is the calibrating voltage for the selcall phase lock in
receive but changes to the PA ALC power adjustment control in transmit. This voltage is varied by the
microprocessor to produce low and high RF power levels from the PA and is also used to trim the PA RF
power output at high temperature. (AN7 on the microprocessor has a temperature sensor on it for this
purpose)
4.1.9
PA ALC control voltage PWR ADJ
PAGE 18
Summary of Contents for 900 Series
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Page 72: ...BARRETT 900 SERIES TRANSCEIVERS Microprocessor PCB overlay showing TCXO PAGE 72 ...
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Page 87: ...BARRETT 900 SERIES TRANSCEIVERS PA PCB overlay PAGE 87 ...
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Page 89: ...BARRETT 900 SERIES TRANSCEIVERS PA schematic See File PA SCHEMATIC pdf PAGE 89 ...
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Page 99: ...BARRETT 900 SERIES TRANSCEIVERS Front panel PCB overlay PAGE 99 ...
Page 103: ...BARRETT 900 SERIES TRANSCEIVERS Remote Control Head PCB overlay PAGE 103 ...
Page 108: ...BARRETT 900 SERIES TRANSCEIVERS Scrambler PCB overlay PAGE 108 ...
Page 111: ...BARRETT 900 SERIES TRANSCEIVERS GPS ALE Motherboard Overlay PAGE 111 ...
Page 112: ...BARRETT 900 SERIES TRANSCEIVERS GPS ALE Motherboard Schematic PAGE 112 900 GPS ALE Schematic ...
Page 114: ...BARRETT 900 SERIES TRANSCEIVERS 950MR Low Pass Filter Power PCB overlay PAGE 114 ...
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Page 121: ...BARRETT 900 SERIES TRANSCEIVERS 980PSU DC DC Switch Mode Power Supply PCB Overlay PAGE 121 ...
Page 139: ...940 Front Metalwork Connection PCB Overlay BARRETT 900 SERIES TRANSCEIVERS PAGE 139 ...
Page 148: ...940 Tuner Front Panel PCB Overlay BARRETT 900 SERIES TRANSCEIVERS PAGE 148 ...
Page 149: ...940 Tuner Front Panel PCB Schematic BARRETT 900 SERIES TRANSCEIVERS PAGE 149 ...