Barrett 900 Series, Technical Manual

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BARRETT 900 SERIES TRANSCEIVERS
4.0 Technical description
The Microprocessor PCB incorporates the microprocessor unit which controls the transceiver system, the
synthesiser, which provides three stable local oscillator sources, the selcall encoder/decoder which
generates and demodulates selcall signals, and the audio syllabic mute and transmitter power control.
The transceiver has several internal voltage regulators to 5 volt and +10 volt supplies used
throughout the transceiver. Where lowest power consumption is required, as in the 940 man-pack, some of
these have a switch mode regulator to replace the normally fitted linear regulators.
On the microprocessor PCB, U19 and U20 can be replaced by a single switch-mode regulator U36. Other
minor components that need to be added are L3, L6 C118, C119, C117, and C121.
The reference oscillator at 45.455 MHz is the master clock which determines the frequency and timing of all
other synchronous events in the transceiver. It consists of active devices Q13 and Q14 configured as a
Butler oscillator. L16 is set to cancel the crystal stray capacitance and L15 resonates with C132, C133 and
C137, C146 to provide fine frequency trimming. The oscillator is trimmed to 1ppm and an oven maintains a
constant crystal temperature. The output of the reference oscillator is fed direct to the second mixer on the
RF/Audio PCB via TP35 and is buffered prior to routing to the digital section by Q10 and Q11. These are
configured in cascode to minimise reverse coupling. Further buffering is obtained from inverter U31:A prior
to feeding the cascade flip flops U32:A and U32:B. These devices provide a 1:1 duty cycle clock for the
DDFS chip U7 at 22.72 MHz and the microprocessor U1 at 11.36 MHz. A further divider U13 yields 2.84
MHz clock for the Carrier Insertion Oscillator generation by the DDFS. Link LK2 must be IN and LK1 must be
OUT for the standard oscillator.
The reference oscillator at 45.455 MHz is the master clock which determines the frequency and timing of all
other synchronous events in the transceiver. It consists of either a modular TXCO or DCXO oscillating at
45.455 MHz. The oscillator frequency is trimmed using the adjustment on the top of the can. The output of
the TCXO is buffered by Q20, then fed direct to the second mixer on the RF/Audio PCB via TP35 and is
buffered prior to routing to the digital section by Q10 and Q11. These are configured in cascode to minimise
reverse coupling. Further buffering is obtained from inverter U31:A prior to feeding the cascade flip flops
U32:A and U32:B. These devices provide a 1:1 duty cycle clock for the DDFS chip U7 at 22.72 MHz and the
microprocessor U1 at 11.36 MHz. A further divider U13 yields 2.84 MHz clock for the Carrier Insertion
Oscillator generation in the DDFS. Link LK2 must be OUT and LK1 must be IN for the high stability oscillator
option.
The microprocessor U1 is the device which executes the control program for the transceiver. It executes
instructions stored in EPROM U4 and stores and reads non-volatile data from EEPROM U5. These are
connected via a sixteen line bus which has low order address and data multiplexed on the same eight lines.
The low address is de-multiplexed using octal latch U2. A security PAL U40 is also fitted on the data bus to
permit configuration security.
Two parallel output ports U15 (I/O Port 1) and U16 (I/O Port 0) handle static and slow logic signals from
microprocessor. These include PA filter select lines, Audio / IF control signals such as PTT, AM on and NB
on, Mic Disable, Speaker clamp and Mute and ATU control signals Tune Clock and Scan Data.
U14 (I/O port 3) is used to input parallel data from U35, a PWM decoder used to input key PCB data from the
front panel and remote head.
Decoding for all these peripheral devices is provided by 3 to 8 decoder U6 along with U3 and U11. Shift
register U17 ensures that the timing for the EEPROM operation is correct.
4.1 Microprocessor PCB
4.1.2 Power supplies
4.1.3 Reference oscillator (Standard)
4.1.4 Reference oscillator (High stability option)
4.1.5 Microprocessor
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