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1.8 Technical Data
25
Figure 6: Rev. 3.x
LED
Name
Description
D9
FPGA state
Green: FPGA is loaded
D10
PCI Express® x4 connection state
Green: No problem with connection (PCI Express host supports 4
lanes)
D24
PCI Express® x1 connection state
Green: No problem with connection (PCI Express host supports 1
lanes)
Connector usage
mvHYPERION
-CLb
-CLe
-CLm
-CLf
J1
Camera 1 (BASE 1)
Camera 1 (BASE 1)
Camera 1 (BASE 1)
Camera 1 (BASE 1)
J2
-
Camera 1 (MEDI
←
-
UM 1) or camera 2
(BASE 2)
Camera 1 (MEDI
←
-
UM 1) or camera 2
(BASE 2)
Camera 1 (MEDI
←
-
UM 1) or camera 1
(FULL 1)
J3
Camera 1 trigger
/ sync / strobe /
power connector
Camera 1 trigger
/ sync / strobe /
power connector
Camera 1 trigger
/ sync / strobe /
power connector
Camera 1 trigger
/ sync / strobe /
power connector
J4
-
Camera 2 trigger
/ sync / strobe /
power connector
Camera 2 trigger
/ sync / strobe /
power connector
Additional
con-
nector with trigger
/ sync / strobe /
power
1.8.1.2.2
Use of J1..J4
1.8.1.2.3
Pinning J1/J2 (CL configuration)
Figure 7: Mini CameraLink connector (female)
Pin J1/J2
(used as) BASE
(used as) MEDIUM
(used as) FULL
Signal
Type
Signal
Type
Signal
Type
1
Internal
shield
or
Power
PoCL
(p.
(+12V
or
Ground)
Internal
shield
or
Power
PoCL
(p.
(+12V
or
Ground)
Internal
shield
or
Power
PoCL
(p.
(+12V
or
Ground)
14
Internal
shield
Ground
Internal
shield
Ground
Internal
shield
Ground
25
X0-
Input 1-
Y0-
Input 1-
Y0-
Input 1-
12
X0+
Input 1+
Y0+
Input 1+
Y0+
Input 1+
24
X1-
Input 2-
Y1-
Input 2-
Y1-
Input 2-
MATRIX VISION GmbH