5. LX1553-5 FEATURES
This section describes the interfaces and features available on the Lx1553-5. If
you need more information than what is presented here, please contact Customer
Service at Ballard Technology for assistance (see Section 1.5).
5.1 PCI/PCIe Bus
The LP1553-5 uses the industry standard PLX Technology’s PCI 9056 which
interfaces the protocol circuitry to the PCI bus. The PCI 9056 provides the
LP1553-5 with many features including:
•
32-bit wide host PCI data bus
•
33/66MHz PCI clock speed
•
Universal signaling voltage on the PCI bus
•
PCI bus mastering
The LE1553-5 uses the industry standard PLX Technology’s PEX 8311 which
interfaces the protocol circuitry to the PCIe bus. The PEX 8311 provides the
LE1553-5 with many features including:
•
PCI Express single-lane (x1) Endpoint
•
Compatible with multi-lane PCIe devices
•
Full 2.5 Gbps per direction
•
PCIe bus mastering
5.2 MIL-STD-1553
Each MIL-STD-1553 channel is available in two levels of functionality
(summarized in Table 5.1). Both levels provide at least Bus Controller, Remote
Terminal, or Monitor operation. Advanced features include concurrent
BC/RT/Monitor operation and protocol error injection (word, gap, and message
errors).
Level Designator
→
S M
BC/RT/MON Operation
Single Multi
BC or 32 RTs or MON
BC and 32 RTs and MON
Protocol Error Injection
Table 5.1—Ballard MIL-STD-1553 Functionality Levels
Lx1553-5 User’s Manual
5-1
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