11
MEMORY
ADDRESS DECODING
Address decoding is accomplished using a GAL16V8 programmable logic device. Address
lines A<8:15>, AS (address strobe), R/W (read/write), and E (clock) are processed to
provide the memory control signals as shown below by default. Custom configurations,
differing from that shown below, are also possible. Contact the factory for assistance in
redefining the memory map if required.
OE
Output enable to U5, U6, and U7
WR
Write enable to U5 direct, and to U6 and U7 through jumpers JP6 and
WRITE_EN respectively.
M1
Chip select to U5 active from 0 to 8K (with mirrored mapping) or 0 to 32k
depending on the status of JP3. See U5 JP3 selection for more information.
M2
Chip select to U6 active for the 24k between 8000 and CFFF, with the
exception of B580 through B7FF inclusive. B580 to B5FF is used to generate
the peripheral chip selects.
M3
Chip select to U7 active for the 8k between E000 and FFFF. Note that U7 is
mapped to the same location as the internal ROM of the HC11.
P
Peripheral Access CS0 - CS7. B580 through B5FF.
All of these signals except P are active low. P is active high. Signal line M2 is also
connected to the BUS_PORT expansion connector allowing M2 to work in conjunction with
the CS and Address lines to implement off board, page banked memory. When M2 is used
in this manner, U6 must be removed from the board.
U5 is intended to be either an 8k or a 32k RAM. U6 can accommodate RAM, EEPROM, or
ROM. U7 is to be used primarily for ROM but it can also accommodate EEPROM. The
ROMON bit in the configuration word must be OFF for U7 to be in the memory map.
Jumpers JP3 through JP9 and WRITE_EN determine how U5, U6, and U7 are used. See
the
Memory Selection Jumpers
section for details.
Peripheral Access 'P' is used in conjunction with A<4:6>, and AS to generate CS<0:7>.
Each of these eight chip selects controls sixteen bytes in the memory map from B580
through B5FF. CS<7:0> are brought out to the BUS_PORT where they can be used to
control peripherals external to the development board. See the Memory Map on the next
page for further clarification.
