Figure A
If the delay is negative, the order of the SYNC and OUT pulses is reversed:
Figure B
The next figure illustrates the relationship between the signal when an external TTL-
level trigger is used:
20
SYNC OUT
(generated by the
internal oscillator)
100 ns, FIXED
MAIN OUTPUT
PULSE WIDTH
DELAY > 0
AMPLITUDE,
VARIABLE
3V, FIXED
OFFSET,
VARIABLE
0V
SYNC OUT
(generated by the
internal oscillator)
100 ns, FIXED
MAIN OUTPUT
PULSE WIDTH
DELAY < 0
AMPLITUDE,
VARIABLE
3V, FIXED
OFFSET,
VARIABLE
0V
Summary of Contents for AVR-D2-B
Page 36: ...PCB 158R4 LOW VOLTAGE POWER SUPPLY...
Page 37: ...PCB 235B HIGH VOLTAGE DC POWER SUPPLY...
Page 38: ...PCB 151D RANGE CONTROL...
Page 44: ...PERFORMANCE CHECK SHEET 44...