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ZedBoard

(

ynq™

valuation and

evelopment

)

Configuration and Booting Guide

Version 1.1

August 2012

Summary of Contents for zedboard

Page 1: ...ZedBoard Zynq Evaluation and Development Configuration and Booting Guide Version 1 1 August 2012 ...

Page 2: ...al Console on a Windows 7 Host 6 JTAG Configuration Mode 7 Application Download 7 GPIO Test Demo 9 SDK Software Tasks 10 Create the SDK Workspace 10 Create the Board Support Package 14 Import the GPIO Test Software Application 16 Running the GPIO Test Software Application 18 Create the First Stage Boot Loader 23 Create the Boot Image 24 Booting From the SD Card 26 Prepare the SD Card 26 GPIO Test ...

Page 3: ... how to use the JTAG configuration mode of the ZedBoard as well as how to boot the processor and configure the programmable logic of the Zynq 7000 device using the SD card and QSPI boot modes The tasks performed in this guide follow a logical progression such that it is expected that users will start at the beginning and work their way toward the end Reference Design Requirements Software The soft...

Page 4: ...e Logic PL bitstream described in the ZedBoard Zynq 7000 EPP Concepts Tools and Techniques hands on guide found at www zedboard org design The following figure shows a high level block diagram of the hardware design The design requires Z7020 Zynq 7000 AP SoC 512MB DDR3 SDRAM 256Mbit QSPI Flash USB UART Bridge Serial Port LEDs and push button switches Timer Figure 1 Reference Design Block Diagram ...

Page 5: ...mands to load the PL bitstream of the hardware design initialize the processor and download the GPIO test application run_uboot bat Batch file to run the commands to initialize the processor and download the u boot application system bit The golden FPGA bitstream of the hardware design required to run the GPIO test application u boot_autoboot_disabled elf The golden ARM executable for the u boot a...

Page 6: ... applications Figure 2 ZedBoard Development Board 1 Verify a jumper is installed on JP6 to enable the processor to boot from the SD card 2 Plug a USB cable into the PC and the JTAG micro B USB connector J17 3 Plug a USB cable into the PC and the UART micro B USB connector J14 4 Plug the 12V power supply into the barrel jack J20 Do not turn the board on JTAG J17 UART J14 Power SW8 Configuration Mod...

Page 7: ...ing the UART Driver and Virtual COM Port If the ZedBoard development board has not been connected to the host PC before it may be necessary to install the software driver for the virtual COM port The driver installation for the Cypress CY7C64225 USB UART bridge is described in detail in the CY7C64225 Setup Guide available at http www zedboard org sites default files CY7C64225_Setup_Guide_1_1 pdf I...

Page 8: ...will see the green power good LED LD13 illuminate 3 Navigate to Control Panel Device Manager Ports COM LPT and identify the COM port connected to the ZedBoard Start a serial terminal session for the identified COM port and set the serial port parameters to 115200 baud rate no parity 8 bits 1 stop bit and no flow control 4 Open a command window in the installation demo folder and enter run_gpio_tes...

Page 9: ...4 1 8 5 The FPGA bitstream will be downloaded followed by the executable file for the software application Do not close the command window 6 When the executable has finished loading and is ready to run you should see the following in your serial terminal window ...

Page 10: ... LED on and off 1 Follow the screen prompts to select the push button input One push button is routed to the AXI GPIO peripheral BTNU and the other is routed to the CPU GPIO BTNR through the EMIO interface between the PS and PL sections Run the application as many times as you wish and alternate which push button is selected Leave the terminal window open when you are done We will reuse this termi...

Page 11: ... application development Here we will import the pre built GPIO test software application that is described in the ZedBoard CTT guide and create the Zynq First Stage Boot Loader FSBL that we will copy to the SD card and boot on the ZedBoard Create the SDK Workspace 1 Start in PlanAhead to generate an empty SDK workspace based on the pre built hardware platform described in the ZedBoard CTT guide N...

Page 12: ...ZedBoard Booting and Configuration Guide ISE Design Suite 14 1 11 2 Navigate to the installation pa project_1 folder and select the project_1 ppr project file Click OK to continue ...

Page 13: ...and display the Flow Navigator and Project Manager view with the Project Summary Select File Export Export Hardware from the PlanAhead GUI 4 Accept the defaults and check the box to Launch SDK Click OK to continue PlanAhead will display the following window while the SDK workspace is created ...

Page 14: ... with just the imported system_hardware_platform similar to the window shown below 6 Make note of the base address for the DDR3 SDRAM ps7_ddr_0 0x00100000 and the QSPI Flash ps7_qspi_0 0xE000D000 We will need to know this when we program the QSPI Flash later when we prepare to boot the ZedBoard in QSPI boot mode ...

Page 15: ...hich individual projects can be built Multiple BSPs and multiple application projects can be held in a single SDK workspace To begin create a basic BSP that is adequate for the GPIO test and FSBL applications we intend to run 1 From the SDK main menu select File New Xilinx Board Support Package 2 Accept the defaults for the Project name Hardware Platform CPU and OS Click Finish to continue ...

Page 16: ...t this point the basic software platform to build general applications for this board has been created We do not need to add additional software libraries to the BSP or change any settings so click OK to continue and the software platform will automatically compile link ...

Page 17: ...pplication is described in the Appendix A of the ZedBoard CTT and is pre built for us to use here Feel free to examine and become familiar with the source code for this application The next step is to import this application so we can build and run it on the board 1 Go to File Import General Existing Projects into Workspace ...

Page 18: ...lder Check the box to Copy projects into workspace and click Finish to continue The software application will automatically build and be added to the SDK workspace At this point the gpio_test_0 application is ready to run but first we must setup the Xilinx Microprocessor Debugger XMD options to download and run the software application ...

Page 19: ...e all pins shunted to GND as in the figure below 2 Slide the power switch SW8 to the ON position You will see the green power good LED LD13 illuminate 3 To prepare for running the gpio_test_0 software application later we will configure the Zynq device with the PL bitstream that includes the AXI timer and GPIO peripherals In the SDK main menu select Xilinx Tools Program FPGA or click on the on the...

Page 20: ...e or ELF file to initialize in Block RAM so accept the default for the system bit file for the PL bitstream that was exported from the PlanAhead hardware project earlier Click Program to continue You will see the following window while the PL bitstream is downloaded Once this is complete the blue DONE LED LD12 will illuminate ...

Page 21: ...ZedBoard Booting and Configuration Guide ISE Design Suite 14 1 20 5 In the Project Explorer window pane select the gpio_test_0 application and right click to select Run As Run Configurations ...

Page 22: ...ide ISE Design Suite 14 1 21 6 Click on the option in the left panel and press the New to create a new Debug run configuration for the gpio_test_0 software application 7 Select the new gpio_test_0 Debug run configuration Click Run continue ...

Page 23: ...can ignore this warning Click OK to continue 9 You should see the following on the serial console 10 You are now ready to run the GPIO test software application The steps to run the application are the same as running the demo you probably used earlier except the steps of downloading the PL bitstream and application executable are already completed Leave the terminal window open when you are done ...

Page 24: ...ill need to create the first stage boot loader application This application is one of the example software applications built into the SDK 1 Go to File New Xilinx C Project to open the window to select from the available example software applications 2 Select the Zynq FSBL project template Accept the defaults for the Project Name and Target Hardware Platform Click Finish to continue ...

Page 25: ...tream at power on we first need to create the boot image to be copied to our boot media The boot image is actually the GPIO test and FSBL application executable files and PL bitstream packaged into a single BOOT BIN file The Zynq boot ROM will look for this file on the boot media It must be named BOOT BIN in upper case letters 1 Go to Xilinx Tools Create Boot Image ...

Page 26: ... or modify the BOOT BIN boot image file b To specify the FSBL elf file click on Browse and navigate to installation pa project_1 project_1 sdk SDK SDK_Export zynq_fsbl_0 Debug and select the zynq_fsbl_0 elf file c To add the PL bitstream click on Add and navigate to installation pa project_1 project_1 sdk SDK SDK_Export system_hw_platform and select the system bit file d To add the GPIO test softw...

Page 27: ...om the SD card 2 In Windows Explorer navigate to installation boot_image and copy the BOOT BIN file to the SD card 3 Turn off the ZedBoard if it is turned on Verify the Configuration Mode jumpers are set for SD card mode as described and in the figure below MODE3 JP10 shunted to 3 3V MODE2 JP9 shunted to 3 3V All other MODE pins shunted to GND 4 Remove the SD card from the PC and insert it in the ...

Page 28: ...on to the application executable When booting from SD card this process may take 10 15 seconds You should see the following on the serial console when the system has completed booting 2 You are now ready to run the GPIO test software application The steps to run the application are the same as running the demo you probably used earlier except the system has now booted from the SD card and the step...

Page 29: ... and that the configuration Mode jumpers are set for JTAG mode all pins shunted to GND as in the figure below 2 Verify the SD card is installed in the ZedBoard We will be copying the BOOT BIN file on the SD card into DDR3 memory and then to QSPI Flash 3 Slide the power switch SW8 to the ON position You will see the green power good LED LD13 illuminate 4 Open a command window in the installation de...

Page 30: ...29 5 The processor will be initialized and the u boot application will be downloaded for the execution Do not close the command window 6 When the u boot executable has finished loading and is ready to run you should see the following in your serial terminal window ...

Page 31: ...ZedBoard Booting and Configuration Guide ISE Design Suite 14 1 30 7 Enter the following commands in the serial terminal window to initialize the SD card and QSPI flash mmcinfo sf probe 0 0 0 ...

Page 32: ...I Flash Strictly speaking this is not necessary but would be a help later if we needed to maximize use of the QSPI flash for other purposes The size of the boot image BOOT BIN is 0x40D930 bytes so we will prepare an area slightly larger Recall earlier when we created the SDK workspace that we made note of the system base address for the DDR3 SDRAM ps7_ddr_0 0x00100000 We need that information now ...

Page 33: ... SD card to DDR3 memory Recall earlier when we created the SDK workspace that we made note of the QSPI Flash ps7_qspi_0 0xE000D000 We need that information now Copy the boot image from the SD card into RAM fatload mmc 0 0x00200000 BOOT BIN The format of this command is fatload interface device RAM address filename ...

Page 34: ...gn Suite 14 1 33 10 Prepare the QSPI Flash We must erase the area of flash first The size of the boot image BOOT BIN is 0x40D930 bytes so we will prepare an area slightly larger sf erase 0 0x410000 The format of this command is sf erase offset length ...

Page 35: ...dBoard Booting and Configuration Guide ISE Design Suite 14 1 34 11 Store the boot image to the QSPI Flash sf write 0x00200000 0 0x410000 The format of this command is sf write source address offset length ...

Page 36: ...in the figure below MODE3 JP10 shunted to 3 3V All other MODE pins shunted to GND 13 Slide the power switch SW8 to the ON position You will see the green power good LED LD13 will illuminate immediately and the blue DONE LED LD12 will illuminate once the processor has been initialized and then configures the PL When booting from QSPI Flash this may take a couple of seconds ...

Page 37: ...RT driver has a chance to load on the host PC This causes the serial terminal window to display a partial GUI or no GUI at all Based on our previous use of this application throughout this boot guide though we know what keys to press to start using the application so proper display of the GUI will resume To start press 1 to use NORMAL GPIO as an input BTNU switch 2 You are now ready to run the GPI...

Page 38: ...Setup Guide www zedboard org sites default files CY7C64225_Setup_Guide_1_1 pdf Concepts Tools and Techniques Guide www zedboard org design Xilinx Website All Zynq Documentation www xilinx com support documentation zynq 7000 htm Zynq 7000 AP SoC Software Developers Guide www xilinx com support documentation user_guides ug821 zynq 7000 swdev pdf Revision History Version Date Author Details 1 0 Augus...

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