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Signal Name
Direction
Pull Up/Pull Down
Description
PR[1:0]
Input
Pull up
Prescaler and Feedback divider control pins.
OD[2:0]
Input
Pull up
Output divider control pins.
OS[1:0]
Input
Pull up
Output type select control pins.
CE
Input
Pull up
Chip enable.
RST_N
Input
Pull up
Device reset (active low).
XIN
Input
Pull up
Parallel resonant crystal/LVCMOS input.
OUT0 P/N
Input
Differential output pair.
Table 9
– CDCM61001 Clock Synthesizer Pin Description
2.4.1.1
CDCM61001 Clock Generation
The CDCM61001 output clocks are generated based on the following formula (assuming
the crystal clock input is 25 MHz):
FOUT = (FIN) (FD) / OD
Equation Variables
:
FOUT
= Output Frequency
FIN
= Clock Input Frequency
FD
= Feedback Divider Value
OD
= Output Divider Value
Please refer to the CDCM61001 datasheet for detailed tables regarding the Feedback
Divider and Output Divider values. The CDCM61001 FD and OD values are programmed
via dipswitches
SW3
and
SW4
. These dipswitches should be configured prior to powering
up the board.
The following table shows how to set the dipswitches for a common application. All the
values are based on a 25 MHz crystal clock input to the CDCM61001 device.
Interconnect
Technology
OUT0 and
OUT1 (MHZ)
PR1
PR0
OD2
OD1
OD0
SATA
150
0
0
0
1
1
GigE
125
1
1
0
1
1
10 GigE
156.25
1
0
0
1
1
12 GigE
187.5
0
1
0
0
1
Table 10
– CDCM61001 Common Application Settings
2.4.1.2
CDCM61001 Programming Mode
The Zynq 7Z045 Mini-Module Plus Development Board allows programming of the PR and
OD values in parallel mode. This is the only mode supported by the device. In parallel
mode, PR and OD values are programmed into the device upon the release of the master
reset signal (rising edge of the MR_N signal). The switches should be set into the correct
position prior to turning on power to the board. Should the switch settings change after
power up the board will have to be power cycled to reset the device.
