30-Oct-2020, Rev. 1.1
7
Table 3 – INIT# Connection
Carrier
Net Name
MicroHeader
Connection
Zynq AP SOC
Connection
INIT#
JX2.9
INIT#
2.3.2
Power On Reset – POR# button – SW2
The POR# button provides an active low signal to the PG_CARRIER net on the JX2
MicroHeader. When asserted, this signal resets the USB UART, USB OTG circuit and
turns off the IOCC VCCIO_34/35 power supplies. It is used to invoke an IOCC and
MicroZed total system power reset. The PS and PL are reset to power on default
settings and the selected boot process is initiated.
Table 4 – POR Connection
Carrier
Net Name
MicroHeader
Connection
Zynq AP SOC
Connection
PG_CARRIER
JX2.11
PG_MODULE
2.3.3
Processor Subsystem Reset: SYS_RST# button – SW4
The SYS_RST# button provides and active low signal to net CARRIER_SRST# which
allows the user to reset all of the functional logic within the device without disturbing the
debug environment. For example, the previous break points set by the user remain
valid after system reset. Due to security concerns, system reset erases all memory
content within the PS, including the OCM. The PL is also reset in system reset.
System reset does not re-sample the boot mode strapping pins.
Table 5 – SYS_RST# Connection
Carrier
Net Name
MicroHeader
Connection
Zynq AP SOC
Connection
CARRIER_SRST#
JX1.6
CARRIER_SRST#
