30-Oct-2020, Rev. 1.1
6
2 Functional Description
The I/O Expansion Carrier Card is an expansion board for Avnet’s MicroZed 7Z010 or
7Z020 System On Module (SOM) product. It adds up to 12 Digilent Pmod™ compatible
Interfaces, 8 User LEDs, 4 User Pushbuttons, 4 DIP Switches and a Xilinx analog
interface.
2.1 Memory – 1Kb SHA Security EEPROM – optional
The Carrier features a footprint for a Maxim 1-Wire SHA-1 Authenticated 1Kb EEPROM,
. The DS28E02 combines 1024 bits of EEPROM with challenge-and-
response authentication security implemented with the FIPS 180-3 Secure Hash
Algorithm (SHA-1).
The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit
scratchpad to perform write operations. All memory pages can be write protected, and
one page can be put in EPROM-emulation mode, where bits can only be changed from a
1 to a 0 state. Each DS28E02 has its own guaranteed unique 64-bit ROM registration
number that is factory installed into the chip.
The DS28E02 communicates over the single-contact 1-Wire® bus. The communication
follows the standard 1-Wire protocol with the registration number acting as the node
address in the case of a multidevice 1-Wire network. Pin 2 of this device must be pulled
high with a 680ohm resistor to VCCio_34.
Table 1 – SHA EEPROM Connection
Carrier
Net Name
MicroHeader
Connection
Zynq AP SOC
Connection
1W-EEPROM
JX1.10
JX_SE_1
2.2 Clock source
A 100 MHz single ended clock is attached to one of the MRCC pins in PL bank 35,
allowing it to connect directly to internal MMCM’s and PLL’s of the Zynq AP SOC. The
FPGA enables this clock via the BB_CLK_EN signal. Default power on state for this clock
is pulled down, thereby off.
Table 2 – 100 MHz Clock Connection
Carrier
Net Name
MicroHeader
Connection
Zynq AP SOC
Connection
BB_CLK
JX2.48
JX2_LVDS_11_P
BB_CLK_EN
JX2.50
JX2_LVDS_11_N
2.3 Reset sources
2.3.1
INIT# button – SW3
The INIT# button provides an active low input signal to the FPGA. It is used to stall the
power-on configuration sequence at the end of the initialization process of the FPGA.
This signal is rarely used.
