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MSC SM2S-IMX8MINI

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User Manual

6 Bus and Address Mapping

6.1 I²C Devices

Table 24: I²C Interfaces Overview

CPU Interface

Device

SMARC Connector

7-bit Address

I2C1

TPM

0x2E

PMIC1

0x31

PMIC2

0x33

Temp. Sensor

0x71

RTC

0x32

PCIe Clock Generator

0x6B

I2C2

I2C_PM

I2C3

Serial EEProm

I2C_GP

0x50

I2C4

I2C_LCD

GPIO

I2C_CAM0

I2C_CAM1

NOTE: CAM0 and CAM1 are GPIO based (bit-banged) and share the same I2C interface.

Summary of Contents for 78368

Page 1: ...SMARC Module MSC SM2S IMX8MINI SMARC Rev 2 0 Standard 30 04 2021 Rev 1 4 User Manual ...

Page 2: ...is not an end user product It was developed and manufactured for further processing by trained personnel Disclaimer Although this document has been generated with the utmost care no warranty or liability for correctness or suitability for any particular purpose is implied The information in this document is provided as is and is subject to change without notice EMC Rules This unit has to be instal...

Page 3: ...ct change notification and end of life management process assures early information of our customers Product Support MSC engineers and technicians are committed to provide support to our customers whenever needed Before contacting Technical Support of MSC Technologies GmbH please consult the respective pages on our web site at https www msc technologies eu support boards html for the latest docume...

Page 4: ...THERMAL SPECIFICATIONS 21 2 1 Thermal Definitions 21 3 MODULE CONNECTOR PINOUT 23 4 MODULE CONNECTOR SIGNAL DESCRIPTION 27 4 1 I S 27 4 2 Ethernet 28 4 3 PCI Express 30 4 4 USB 30 4 5 Camera 32 4 6 LVDS 33 4 7 SPI Bus 35 4 8 CAN 37 4 9 GPIO 38 4 10 SDIO 39 4 11 UART 40 4 12 I C Bus 41 4 13 Watchdog 43 4 14 System Management 43 4 15 Boot Options 45 5 FUNCTIONS ON MODULE 47 5 1 CPU Options 47 5 2 Po...

Page 5: ...Terms 58 7 2 2 Getting Started 58 7 2 3 Setup the MSC LDK build environment 60 7 2 4 Generate images 68 7 2 5 Image Deployment 71 7 3 Running an Image 71 7 3 1 Booting SPL secondary program loader U Boot 71 7 3 2 Booting OS 74 7 3 3 Login to FS 80 7 3 4 SMARC GPIO access 80 7 3 5 Bug Reporting 81 7 4 Hotfixes and updating MSC LDK 85 8 TROUBLESHOOTING 87 8 1 Known issues and limitations 87 8 1 1 Is...

Page 6: ...for MSC LDK Part 1 64 Figure 7 8 Prepare docker container for MSC LDK Part 2 64 Figure 7 9 Prepare docker container for MSC LDK Part 3 65 Figure 7 10 Start and enter the MSC LDK container 65 Figure 7 11 Leave the MSC LDK container 66 Figure 7 12 Re start and re enter the MSC LDK container 66 Figure 7 13 Stop the MSC LDK container and release its resources 67 Figure 7 14 Building msc image qt5 imag...

Page 7: ... Table 13 CAN Signal Description 37 Table 14 GPIO Signal Description 38 Table 15 SDIO Signal Description 39 Table 16 UART Signal Description 41 Table 17 I C Signal Description 42 Table 18 Watchdog Signal Description 43 Table 19 System Management Signal Description 43 Table 20 Boot Options Control Signal Description 45 Table 21 Boot Options 46 Table 22 Available SDRAM options 50 Table 23 Available ...

Page 8: ... History Rev Date Description 1 0 July 31 2020 First Release 1 1 September 16 2020 Added comment in section EEPROM 1 2 February 10 2021 Bug fix 1 3 March 17 2021 Fix USB Boot option and Section 2 1 1 4 April 30 2021 Corrected Section 4 5 Camera ...

Page 9: ...INI pdf https www msc technologies eu products solutions products boards smarc msc sm2s imx8mini html 5 i MX Yocto Project User s Guide i MX_Yocto_Project_User s_Guide pdf Rev L4 19 35_1 1 0 11 2019 http www nxp com 6 i MX Reference Manual i MX_Reference_Manual pdf Rev L4 19 35 1 1 0 11 2019 http www nxp com 7 i MX Linux User s Guide i MX_Linux_User s_Guide pdf Rev L4 19 35_1 1 0 11 2019 http www ...

Page 10: ...MSC SM2S IMX8MINI 10 87 User Manual 9 Docker documentation https docs docker com ...

Page 11: ... connector Due to the standardized mechanics and interfaces the system can be scaled arbitrarily Despite the modular concept the system design is very flat and compact SMARC modules require a carrier board to build a working system For evaluation purposes MSC recommends the MSC SM2 MB EP1 Evaluation Board 1 1 Key Features SoC NXP i MX8M Mini ARM CORTEX A53 Assembly options for i MX8M Mini single d...

Page 12: ...Ethernet Optional H D Wireless Module SPB209A with 802 11 ac a b g n and Bluetooth 4 2 with BLE support USB 1x USB2 0 Host Port with device Interface capability and on the go OTG support 1x USB2 0 Host Port or 4x USB2 0 Host Ports with additional USB hub populated on module GPIO 12x GPIO configurable as input or output push pull or open drain SPI 2x SPI with 2 chip selects each ...

Page 13: ... C bus for camera interface UART 2x UART without RTS CTS support 2x UART with RTS CTS support Flash Up to 64GByte eMMC NAND flash Optional 32Mbit QSPI NOR Flash Storage Interface 1bit 4bit SD SDIO MMC Interface Optional on module microSD Card Socket EEPROM 64Kbit EEPROM for module information and user applications CAN Optional 2x CAN 2 0B up to 1Mbps ...

Page 14: ... STMicroelectronics ST33TPHF20I2C Environment Temperature 0 70 C all components commercial temp or better 40 85 C all components industrial temp 40 85 C storage Environment Humidity 5 95 operating 5 95 storage NOTES the second Ethernet interfaces makes use of the PCIe interface so the PCIe Lane is not available when second Ethernet is populated mutually exclusive assembly option microSD card socke...

Page 15: ... IMX8MINI 15 87 User Manual The SPI interface s are used to implement the optional CAN interface s and so are mutually exclusive options If two CAN controllers are used then the two SPI buses are not available ...

Page 16: ...MSC SM2S IMX8MINI 16 87 User Manual 1 2 Block Diagram Figure 1 1 Block Diagram ...

Page 17: ... 1 5V 5 5V Max Input Ripple 20mV Current 0 18µA typ VDD 3V 1µA max GND Power and signal return path All available GND connector pins shall be connected and tied to Carrier Board GND plane 1 4 Power Consumption 1 4 1 Use Cases Uboot Idle Ethernet link established no display used no USB devices Linux Idle Ethernet link established no display used no USB devices Linux Heavy Load CPU load 100 on each ...

Page 18: ... PCBFTX i MX8M Mini Solo Single Core Cortex A53 at 1 8GHz 1G LPDDR4 40 C to 85 C 78406 MSC SM2S IMX8MINISCL 03N0880I PCBFTX i MX8M Mini Solo Lite Single Core Cortex A53 at 1 8GHz 1G LPDDR4 40 C to 85 C 1 4 3 Measurement Results Table 3 Typical Power Consumption Measurement Order Number Reference Uboot Idle W Linux idle W Linux Heavy Load W Deep Sleep W 78402 MSC SM2S IMX8MINIQC 14N0261I PCBFTX 2 0...

Page 19: ... 2 Module Dimensions Figure 1 3 Overall height without heat spreader of the SMARC Module The overall height is dependent on the MXM3 connector used on the baseboard Carrier PCB Module PCB 1 2mm BOT Side Component 1 3mm max TOP Side Component 3 0mm max 1 5mm min 5 7mm min ...

Page 20: ... may result in a slight mechanical bending of the SMARC module PCB Production tolerance material deviation and thermal expansion lead to a range of possible pressure range and bending A negative pressure with an air gap between the heat spreader and the chip case needs to be avoided and likewise too much distortion Component types and their distance to the heat spreader mounting holes need to be c...

Page 21: ...s that each device on the module is operated within its specified thermal limits There may be system implementations where the heat spreader temperature could be higher In such a case the cooling solution design should be validated such that the thermal specifications of all the components on the module are not violated across the system operating temperature range even under worst case conditions...

Page 22: ...mperature range in the following table Table 4 Temperature Range Module Variant Tpcb_min Tpcb_max Module variants with commercial temperature components 0 C 70 C Module variants with extended temperature components 25 C 85 C Module variants with industrial temperature components 40 C 85 C Figure 2 1 Defined Temperature Point ...

Page 23: ... P11 CSI1_RX1 S11 CSI0_RX0 P12 GND S12 CSI0_RX0 P13 CSI1_RX2 S13 GND P14 CSI1_RX2 S14 CSI0_RX1 P15 GND S15 CSI0_RX1 P16 CSI1_RX3 S16 GND P17 CSI1_RX3 S17 GBE1_MDI0 Primary Top Side Secondary Bottom Side P18 GND S18 GBE1_MDI0 P19 GBE0_MDI3 S19 GBE1_LINK100 P20 GBE0_MDI3 S20 GBE1_MDI1 P21 GBE0_LINK100 S21 GBE1_MDI1 P22 GBE0_LINK1000 S22 GBE1_LINK1000 P23 GBE0_MDI2 S23 GBE1_MDI2 P24 GBE0_MDI2 S24 GBE...

Page 24: ...8 I2C_GP_CK P49 NC S49 I2C_GP_DAT P50 GND S50 I2S2_LRCK P51 NC S51 I2S2_SDOUT P52 NC S52 I2S2_SDIN P53 GND S53 I2S2_CK P54 SPI1_CS0 S54 NC P55 SPI1_CS1 S55 NC Primary Top Side Secondary Bottom Side P56 SPI1_CK S56 NC P57 SPI1_DIN S57 NC P58 SPI1_DO S58 NC P59 GND S59 NC P60 USB0 S60 NC P61 USB0 S61 GND P62 USB0_EN_OC S62 NC P63 USB0_VBUS_DET S63 NC P64 USB0_OTG_ID S64 GND P65 USB1 S65 NC P66 USB1 ...

Page 25: ... GND P92 NC S93 NC P93 NC S94 NC P94 GND S95 NC P95 NC S96 NC Primary Top Side Secondary Bottom Side P96 NC S97 NC P97 GND S98 NC P98 NC S99 NC P99 NC S100 NC P100 GND S101 GND P101 NC S102 NC P102 NC S103 NC P103 GND S104 NC P104 NC S105 NC P105 NC S106 NC P106 NC S107 LCD1_BKLT_EN P107 NC S108 LVDS1_CK DSI1_CLK P108 GPIO0 S109 LVDS1_CK DSI1_CLK P109 GPIO1 S110 GND P110 GPIO2 S111 LVDS1_0 DSI1_D0...

Page 26: ...VDS0_2 DSI0_D2 P132 SER0_CTS S133 LCD0_VDD_EN P133 GND S134 LVDS0_CK DSI0_CLK P134 SER1_TX S135 LVDS0_CK DSI0_CLK P135 SER1_RX S136 GND P136 SER2_TX S137 LVDS0_3 DSI0_D3 P137 SER2_RX S138 LVDS0_3 DSI0_D3 Primary Top Side Secondary Bottom Side P138 SER2_RTS S139 I2C_LCD_CK P139 SER2_CTS S140 I2C_LCD_DAT P140 SER3_TX S141 LCD0_BKLT_PWM P141 SER3_RX S142 NC P142 GND S143 GND P143 CAN0_TX S144 NC P144...

Page 27: ...ogrammable word length 16 20 24 or 28bits AC97 and TDM support Time Slot Mask Registers for reduced ARM platform overhead for both Transmit and Receive 128 word Transmit FIFO and 128 word Receive FIFO Table 6 I S Signal Description Signal Pin Type Signal Level Pin on i MX8M Mini Pin name on i MX8M Mini Power Tolerance PU PD Description I2S0_LRCK O PP 1 8V CMOS AC14 SAI5_RXD1 1 8V Sample synchroniz...

Page 28: ...e and can be left unconnected Both Ethernet Controller have built in termination resistors As a result no external termination resistors should be used Please refer to the DP83867EVM schematics for correct magnetics wiring Each Center tap of the magnetics should be independently de coupled to ground via a 0 1µF capacitor Table 7 Ethernet Signal Description Signal Pin Type Signal Level Pin on i MX8...

Page 29: ...I O Analog n a n a 3 3V Media Dependent Interface Differential Pair 1 Used for the transmit pair in 10 100 Mbit s mode GBE1_MDI2 GBE1_MDI2 I O Analog n a n a 3 3V Media Dependent Interface Differential Pair 2 This signal pair is only used for 1000Mbit s mode GBE1_MDI3 GBE1_MDI3 I O Analog n a n a 3 3V Media Dependent Interface Differential Pair 3 This signal pair is only used for 1000Mbit s mode G...

Page 30: ... PCIE_CLK_N PCIE_CLK_P According to PCIe spec PCI Express Reference Clock AC coupled on module Clock enabled by default PCIE_WAKE I 3 3V CMOS N27 NAND_RE_B 3 3V PU 10k PCI Express Wake signal Asserted by device when requesting wake up CPU GPIO3_IO15 PCIE_A_RST O PP 3 3V CMOS K27 NAND_CLE 3 3V PCI Express Reset output signal NOTE In case GBE1 Interface is implemented on the module the PCIe Interfac...

Page 31: ...B 2 0 data pairs connected to USB hub Can be configured as host only USB0_VBUS_DET 1 2 I Analog F22 USB1_VBUS 5V external VBUS detection pin USB0_OTG_ID 1 2 I 3 3V CMOS D22 USB1_ID 3 3V PU 10k 3 3V USB host client control select pin for the USB controller on the module USB0_EN_OC 1 2 I O OD 3 3V CMOS AB10 GPIO1_IO12 3 3V PU 10k 3 3V Host client dependent enable signal for USB power switch on the c...

Page 32: ...EN_OC should be left unconnected 4 5 Camera MIPI CSI 2 interface is supported on CSI0 with 2 lanes or on CSI1 with 4 lanes mutually exclusive assembly option Table 10 HDMI Signal Description Signal Pin Type Signal Level Pin on i MX8M Mini Pin name on i MX8M Mini Power Tolerance PU PD Description CSI0_RX 0 CSI0_RX 0 I 1 8V CMOS A14 B14 MIPI_CSI_D0_N MIPI_CSI_D0_P 1 8V CSI differential data inputs C...

Page 33: ...V CAM0 DDC clock line CPU GPIO5_IO24 I2C_CAM1_DAT I O OD 1 8V CMOS E15 UART2_TXD 1 8V PU 2 2k 1 8V CAM1 DDC data line CPU GPIO5_IO25 CAM0_PWR I O OD 1 8V CMOS AG14 GPIO1_IO00 1 8V PU 470k 1 8V CAM0 Power Enable active low GPIO0 alternate use CAM1_PWR I O OD 1 8V CMOS AF14 GPIO1_IO01 1 8V PU 470k 1 8V CAM1 Power Enable active low GPIO1 alternate use CAM0_RST I O OD 1 8V CMOS AF13 GPIO1_IO03 1 8V PU...

Page 34: ...VDS Channel 0 differential pair LVDS0_2 DSI0_D2 LVDS0_2 DSI0_D2 O LVDS n a n a 2 8V LVDS Channel 0 differential pair LVDS0_3 DSI0_D3 LVDS0_3 DSI0_D3 O LVDS n a n a 2 8V LVDS Channel 0 differential pair LVDS0_CK DSI0_CLK LVDS0_CK DSI0_CLK O LVDS n a n a 2 8V LVDS Channel 0 differential clock LVDS1_0 DSI1_D0 LVDS1_0 DSI1_D0 O LVDS n a n a 2 8V LVDS Channel 1 differential pair LVDS1_1 DSI1_D1 LVDS1_1...

Page 35: ...enable CPU GPIO4_IO14 LCD1_BKLT_PWM O PP 1 8V CMOS AG9 SPDIF_RX 1 8V PD 10k LCD1 backlight brightness control PWM2_OUT I2C_LCD_CK O PP 1 8V CMOS D13 I2C4_SCL 1 8V PU 2 2k 1 8V I C clock output for LVDS display use I2C_LCD_DAT I O OD 1 8V CMOS E13 I2C4_SDA 1 8V PU 2 2k 1 8V I C data line for LVDS display use NOTE LCD1_VDD_EN LCD1_BKLT_EN and LCD1_BKLT_PWM can be left unconnected in case dual link L...

Page 36: ..._MISO 1 8V Master Input Slave Output SPI0_DO O PP 1 8V CMOS B7 ECSPI1_MOSI 1 8V Master Output Slave Input SPI0_CK O PP 1 8V CMOS D6 ECSPI1_SCLK 1 8V Clock Output SPI0_CS0 O PP 1 8V CMOS B6 ECSPI1_SS0 1 8V PU 10k 1 8V Chip Select 0 SPI0_CS1 O PP 1 8V CMOS AD22 SAI2_TXC 1 8V PU 10k 1 8V Chip Select 1 GPIO4_IO25 SPI1_DIN I 1 8V CMOS A8 ECSPI2_MISO 1 8V Master Input Slave Output SPI1_DO O PP 1 8V CMOS...

Page 37: ...re supported time triggered protocols data byte filtering and one shot mode Table 13 CAN Signal Description Signal Pin Type Signal Level Pin on i MX8M Mini Pin name on i MX8M Mini Power Tolerance PU PD Description CAN0_TX O 1 8V CMOS n a n a 1 8V CAN Transmit output CAN0_RX I 1 8V CMOS n a n a 1 8V CAN Receive input CAN1_TX O 1 8V CMOS n a n a 1 8V CAN Transmit output CAN1_RX I 1 8V CMOS n a n a 1...

Page 38: ...0k 1 8V CPU GPIO1_IO03 GPIO3 CAM1_RST I O 1 8V CMOS AF12 GPIO1_IO05 1 8V PU 470k 1 8V CPU GPIO1_IO05 GPIO4 HDA_RST I O 1 8V CMOS AG11 GPIO1_IO05 1 8V PU 470K 1 8V CPU GPIO1_IO06 GPIO5 PWM_OUT I O 1 8V CMOS AD6 SAI3_MCLK 1 8V PU 470K 1 8V CPU GPIO5_IO02 PWM4_OUT GPIO6 TACHIN I O 1 8V CMOS AF6 SAI3_TXD 1 8V PU 470K 1 8V CPU GPIO5_IO01 GPIO7 I O 1 8V CMOS AB22 SAI2_RXC 1 8V PU 470K 1 8V CPU GPIO4_IO2...

Page 39: ...3V 1V8 CMOS V23 SD2_DATA3 3 3V 1 8V PU 10k 3 3V 1 8V SDIO Controller Data SDIO_CMD I O 3 3V 1V8 CMOS W24 SD2_CMD 3 3V 1 8V PU 10k 3 3V 1 8V SDIO Controller Command SDIO_CK O 3 3V 1V8 CMOS W23 SD2_CLK 3 3V 1 8V PU 10k 3 3V 1 8V SDIO Controller Clock SDIO_PWR_EN O PP 3 3V CMOS AB26 SD2_RESET_B 3 3V PU 10k 3 3V SDIO Controller Power enable SDIO_CD I 3 3V 1V8 CMOS AA26 SD2_CD_B 3 3V 1 8V PU 10k 3 3V 1...

Page 40: ...rogrammable parity even odd and no parity Hardware flow control support for request to send RTS_B and clear to send CTS_B signals RS 485 driver direction control via CTS_B signal Edge selectable RTS_B and edge detect interrupts Status flags for various flow control and FIFO states Voting logic for improved noise immunity 16x oversampling Transmitter FIFO empty interrupt suppression UART internal c...

Page 41: ...8V UART transmit data SER2_RX I 1 8V CMOS AC6 SAI3_TXFS 1 8V PU 10k 1 8V UART receive data SER2_RTS O 1 8V CMOS AF7 SAI3_RXD 1 8V PU 10k 1 8V UART handshake ready to receive data SER2_CTS I 1 8V CMOS AG7 SAI3_RXC 1 8V PU 10k 1 8V UART handshake ready to send data SER3_TX O 1 8V CMOS F18 UART4_TXD 1 8V PU 10k 1 8V UART transmit data SER3_RX I 1 8V CMOS F19 UART4_RXD 1 8V PU 10k 1 8V UART receive da...

Page 42: ...n interrupt Start and stop signal generation detection Repeated Start signal generation Acknowledge bit generation detection Bus busy detection Data rates up to 100kbits s in Standard mode and 400kbits s in Fast mode Table 17 I C Signal Description Signal Pin Type Signal Level Pin on i MX8M Mini Pin name on i MX8M Mini Power Tolerance PU PD Description I2C_GP_CK O OD 1 8V CMOS E10 I2C2_SCL 1 8V PU...

Page 43: ...age divider Should be driven by OD part on carrier CARRIER_PWR_ ON O PP 1 8V CMOS n a n a 1 8V Carrier board circuits should not be powered up until module asserts this signal CARRIER_STBY O PP 1 8V CMOS n a n a 1 8V Module asserts this signal to indicate standby power state RESET_OUT O PP 1 8V CMOS AD19 SAI2_MCLK 1 8V General purpose reset for carrier board CPU GPIO4_IO27 RESET_IN I OD 1 8V CMOS ...

Page 44: ...from Carrier board May be sourced from user Sleep button or Carrier logic Carrier to float the line in in active state Driven by OD part on Carrier Pulled up on module CPU GPIO4_IO09 LID I OD 1 8V CMOS AB18 SAI1_MCLK 1 8V PU 10k 1 8V Lid open close indication to Module Low indicates lid closure Carrier to float the line in in active state Active low level sensitive Pulled up on Module Driven by OD...

Page 45: ... on Module Driven by OD part on Carrier CPU GPIO4_IO18 BOOT_SEL2 I OD 1 8V CMOS AF22 SAI1_TXD5 1 8V PU 10k 1 8V Input straps determine the module boot device Pulled up on Module Driven by OD part on Carrier CPU GPIO4_IO17 FORCE_RECOV I OD 1 8V CMOS n a n a 1 8V PU 10k 1 8V Pulled up on Module Driven by OD part on Carrier TEST I OD 1 8V CMOS n a n a 1 8V PU 10k 1 8V Active low signal for test mode ...

Page 46: ...decide where to boot the Operating System from See table below If FORCE_RECOV signal is pulled low at carrier the module boots via USB Client Mode this feature is only intended for recovery and requires dedicated software from NXP For normal operation do not pull FORCE_RECOV signal low Table 21 Boot Options BOOT_SEL2 BOOT_SEL1 BOOT_SEL0 Boot Source 0 GND GND GND Carrier SATA not supported 1 GND GN...

Page 47: ... Integrated MSC 5 2 Power Up Behaviour The module will behave in the following ways When coming from complete power off 5V unpowered the module will boot if VIN_PWR_BAD or TEST is not low and 5V is present When OS is shut down and 5V is still powered a power button press is required to restart the module If the module does not come up in test mode or force recovery mode it fetches the OS and the f...

Page 48: ... up Sequence Figure 5 2 Power On Timings Time Slot Description Value T1 CARRIER_PWR_ON to VIN_PWR_BAD timing 10 8ms T2 RESET_OUT to CARRIER_PWR_ON 355ms VIN_PWR_BAD Carrier to Module CARRIER_PWR_ON Module to Carrier CARRIER_STBY Module to Carrier RESET_OUT Module to Carrier T1 T2 ...

Page 49: ... system reset RESET_IN assertion leads to a module power cycle as shown in the following figure Figure 5 3 Reset Sequencing Figure 5 4 Reset Timings Time Slot Description Value T1 CARRIER_PWR_ON to RESET_IN timing 10 8ms T2 RESET_OUT to CARRIER_PWR_ON 355ms RESET_IN Carrier to Module CARRIER_PWR_ON Module to Carrier CARRIER_STBY Module to Carrier RESET_OUT Module to Carrier T1 T2 ...

Page 50: ...nd Quad 64 bit Interface 1 GB 2x 32Mx16x8B 64 bit Interface 2 GB 4x 32Mx16x8B 64 bit Interface 4 GB 4x 64Mx16x8B 5 3 2 eMMC Up to 64GB eMMC are supported The eMMC is used in 8 bit mode Table 23 Available eMMC devices Memory Size Technology Operating Temperature Chip Identification Extended 8 GB 15nm X2 eMLC 25 C to 85 C SDINBDG4 8G I1 16 GB 15nm X2 eMLC 25 C to 85 C SDINBDG4 16G I1 32 GB 15nm X2 e...

Page 51: ...rmine the exact board variant and set necessary parameters Make sure to leave this EEPROM in place and DO NOT block address 0x50 on the I2C_GP Bus with other devices otherwise the module will be unable to boot The Board information structure occupies the first 0x80 bytes inside the EEPROM The remaining upper range starting at offset 0x80 is freely available for customer purposes When making use of...

Page 52: ...S Soft AP and Wi Fi Direct Extensive DMA hardware support for data flow to reduce CPU load NOTE microSD card socket and WiFi BT module are mutually exclusive assembly options 5 6 MicroSD Card Socket An optional on module microSD card socket is connected via SDHC3 interface The interface only supports High Speed HS Mode at 50MHz frequency and data rates up to 25MB s 3 3V operation only 5 7 Debug Op...

Page 53: ...h MSC UART debug adapter Serial signals on the Debug connector are at 3 3V TTL level Pinout 1 Ground 2 NC 3 NC 4 NC 5 UART_TXD 6 UART_RXD 7 RESET_IN 8 VCC_3V3 MSC Debug Adaptor 40402 Debug UART Adapter for i MX8 based SMARC Qseven and nanoRISC modules with 8 pin FFC cable to connect COM module to 9 pin D Sub connector Use top top cables 1 ...

Page 54: ...ng the U Boot Linux console depending on availability and usage of the port on the target Carrier board either connection via the Carrier board SMARC connector or via the Debug connector on the module can be chosen to the same effect 5 7 2 JTAG Connector JTAG access to the IMX8M Mini CPU is possible via a 10pin FFC connector The JTAG Chain only contains the CPU itself so all suitable JTAG debugger...

Page 55: ...TAG debug adapter Pinout 10 VCC_1V8 9 JTAG_TRST 8 JTAG_TDI 7 JTAG_TDO 6 JTAG_TMS 5 JTAG_TCK 4 JTAG_MOD 3 NC 2 RESET_IN 1 Ground MSC JTAG Adaptor FFC 10pol 68948 Debug JTAG Adapter for i MX8 based SMARC modules with 10 pin FFC cable to connect COM module to connectors for JTAG connection to Lauterbach and or Goepel debuggers Use top top cables 1 ...

Page 56: ...Overview CPU Interface Device SMARC Connector 7 bit Address I2C1 TPM 0x2E PMIC1 0x31 PMIC2 0x33 Temp Sensor 0x71 RTC 0x32 PCIe Clock Generator 0x6B I2C2 I2C_PM I2C3 Serial EEProm I2C_GP 0x50 I2C4 I2C_LCD GPIO I2C_CAM0 I2C_CAM1 NOTE CAM0 and CAM1 are GPIO based bit banged and share the same I2C interface ...

Page 57: ... AD22 SAI2_TXC CAN0 Controller Dedicated chip select for CAN0 Controller ECSPI2 CS0 A6 ECSPI1_SS0 SPI1_CS0 CS1 AC22 SAI2_TXD0 SPI1_CS1 GPIO based chip select CPU GPIO4_IO26 CS1 AC22 SAI2_TXD0 CAN1 Controller Dedicated chip select for CAN1 Controller QSPI_A CS0 N24 NAND_CE0_B QSPI NOR Flash Dedicated chip select for QSPI NOR Flash NOTE SPI 0 1 _CS1 are not available if the CAN interfaces are implem...

Page 58: ... that is part of a Linux image is called a package A package is generated from sources by a recipe which is a description of where to download the sources and how to compile them within Yocto A layer is a collection of recipes They are stackable and can extend or modify recipes defined in other layers A BSP provides the necessary layers to MSC LDK to support the target s hardware MSC LDK is mainly...

Page 59: ...sers may apply for specific Git repositories by sending an email with their public SSH key and desired project name to mailto support msc technologies eu 7 2 2 3 Creating SSH key If there is no SSH key already available ssh id_rsa pub it can be generated with following command ssh keygen t rsa Example Figure 7 1 RSA key generation Share the public key in ssh id_rsa pub with MSC during Git registra...

Page 60: ... 2 2 4 Configuring HTTP proxy Some source files will be downloaded from HTTP and FTP servers If a proxy must be used these environment variables have to be set export http_proxy http my proxy 3128 export https_proxy http my proxy 3128 export ftp_proxy http my proxy 3128 Note Replace my proxy with the appropriate address of your network s proxy Port number 3128 may also vary depending on your netwo...

Page 61: ...lite msc git02 msc ge com 9418 msc_ol99 msc ldk branch v1 5 0 msc ldk v1 5 0 cd msc ldk v1 5 0 Example Figure 7 2 Clone base MSC LDK repo Your current directory now contains the following sub directories Figure 7 3 Initial content of the root MSC LDK directory 7 2 3 1 2 Step 2 Create build directory To create your build directory run the following command setup sh bsp 0103801 checkout layers ...

Page 62: ...l The 0103801 refers to the MSC LDK for the SM2S i MX8MMini module Example Figure 7 4 Create build directory Your current directory now contains the following sub directories Figure 7 5 Base directory content after setup build directory ...

Page 63: ...r group Using docker may especially be helpful under newer versions of the host s OS such as Ubuntu 18 04 LTS or higher For detailed information about docker installation container handling and development under docker please take a look at 9 7 2 3 2 1 Step 1 Create MSC LDK container Execute git clone ssh gitolite msc git02 msc ge com 9418 msc_ol99 docker msc ldk cd docker msc ldk git checkout v1 ...

Page 64: ...MSC SM2S IMX8MINI 64 87 User Manual Example Figure 7 7 Prepare docker container for MSC LDK Part 1 Figure 7 8 Prepare docker container for MSC LDK Part 2 ...

Page 65: ...er run privileged t i dns nmcli f IP4 DNS m multiline device show 2 1 sed rn s IP4 DNS 1 1 p name msc ldk h docker v pwd src src msc ldk bin bash Example Figure 7 10 Start and enter the MSC LDK container 7 2 3 2 3 Step 3 Clone and enter the base MSC LDK repo See 7 2 3 1 1 7 2 3 2 4 Step 4 Create build directory See 7 2 3 1 2 7 2 3 2 5 Step 5 Enter build directory See 7 2 3 1 3 ...

Page 66: ... LDK container 7 2 3 2 7 Re start and re enter the MSC LDK container Execute docker container start msc ldk docker container exec ti msc ldk bin bash Example Figure 7 12 Re start and re enter the MSC LDK container 7 2 3 2 8 Stop the MSC LDK container and release its resources Execute docker stop msc ldk docker rm msc ldk ...

Page 67: ...MSC SM2S IMX8MINI 67 87 User Manual Example Figure 7 13 Stop the MSC LDK container and release its resources ...

Page 68: ...x size comment msc image base 612MiB A small Wayland GUI image with full target device hardware support Contains MSC features tools msc image qt5 2 3GiB A Wayland GUI image with full target device hardware support Contains Qt5 Qml gstreamer opencv and MSC features tools 7 2 4 2 Building an Image with MSC LDK The MSC LDK build uses the build sh bitbake component command where component can be image...

Page 69: ...ecipes use an echo e somewhat command bitbake calls the buildscripts with bin sh as shell If your hostsystem uses bash as bin sh everything works fine But if a shell with less functionality like dash is used it is necessary to setup bash as sh This can be done on most debian derivated systems by user devhost sudo dpkg reconfigure dash The subsequent question has to be answered with no ...

Page 70: ...1 32 0 When compiling an image yocto also prints the used GIT layer versions see Fehler Verweisquelle konnte nicht gefunden werden For further improvement MSC LDK has these additional features to recreate the image after it has been built and shipped The used layers and the setup line how the BSP was configured is stored in the image s file etc version_layer After compilation the file can be also ...

Page 71: ... 7 2 5 1 Flashing an SD card image To flash an SD card image run the following command sudo dd if image name sdcard of dev sd partition bs 4MiB conv fsync 7 3 Running an Image 7 3 1 Booting SPL secondary program loader U Boot The TEST pin is used to select one of the following boot schema 7 3 1 1 TEST LOW Forced booting SPL U Boot from carrier SD card With TEST LOW e g on MSC SM2 MB EP1 Carrier Bo...

Page 72: ...SC SM2 MB EP1 Carrier Board Test Mode Select DIP Switch OFF the iMX8MMini Boot ROM code uses the module eMMC flash as primary and the carrier SD card as secondary fallback boot media The fall back media is always selected when booting from primary media is not possible empty corrupted etc Figure 7 18 SPL boot selector on EP1 carrier board S2801 eMMC flash boot mode default Example ...

Page 73: ...MSC SM2S IMX8MINI 73 87 User Manual Figure 7 19 SPL boot from module eMMC flash 7 3 1 3 Booting SPL from USB Not supported yet ...

Page 74: ...ier SD card Carrier SD Card Boot Mode BOOT_SEL0 BOOT_SEL1 BOOT_SEL2 Dip Switches on SM2 MB EP1 HIGH LOW LOW Table 27 Carrier SD Card Boot Mode In this configuration the Linux kernel image Image and the device tree blob are loaded from the first partition on the carrier SD card The second partition contains the Linux file system FS ext4 Example Figure 7 20 Booting OS linux from on carrier SD card ...

Page 75: ...Dip Switches on SM2 MB EP1 LOW HIGH HIGH Table 28 eMMC Boot Mode In this configuration the Linux kernel image Image and the device tree blob are loaded from the first partition on the module eMMC flash The second partition contains the Linux file system FS ext4 Example Figure 7 21 Booting OS linux from on module eMMC flash ...

Page 76: ...e and the device tree blob are loaded from the TFTP and the Linux file system is mounting on NFS Server on LAN Depending on your local network infrastructure set the following environment variables at the U Boot prompt setenv serverip TFTP NFS server IP setenv nfsroot nfs root path on NFS server saveenv Example Figure 7 22 Preparing U Boot environment for net boot Then continue system boot with Bo...

Page 77: ...MSC SM2S IMX8MINI 77 87 User Manual Example ...

Page 78: ... USB Boot Mode BOOT_SEL0 BOOT_SEL1 BOOT_SEL2 Dip Switches on SM2 MB EP1 HIGH HIGH HIGH Table 30 USB Boot Mode In this configuration the Linux kernel image Image and the device tree blob are being loaded from the first partition on the USB The second partition contains the Linux file system FS ext4 Example ...

Page 79: ...0I lvds p251hvn01 for 03N4200I variant based systems with AUO P215HVN01 1920x1080 dual channel LVDS panel msc sm2s imx8mm 03N4210I headless for 03N4210I variant based headless systems msc sm2s imx8mm 03N4210I lvds am800480n7 for 03N4210I variant based systems with Ampire AMA 800480N7 800x480 single channel LVDS panel msc sm2s imx8mm 03N4210I lvds ama121a01 for 03N4210I variant based systems with A...

Page 80: ...gin is enabled via serial console 115200 baud 8 bits no parity All images also have telnet login enabled Table 32 Available user accounts account password comment root mscldk root user msc msc standard user with sudo permissions 7 3 4 SMARC GPIO access According to 1 following GPIOs are available on sms2 imx8mmini module Table 33 Available SMARC GPIOs SMARC GPIO IMX GPIO Linux U Boot idx mscio cmd...

Page 81: ...hapter 2 1 5 6 1 GPIO Hardware Operation chapter 2 1 6 General Purpose Input Output GPIO 7 3 5 Bug Reporting To simplify collecting information necessary for effectively responding to bug reports please use the msc_bug_report sh tool to generate bug report message It will collect all necessary information like hardware description configuration kernel logs etc Run msc_bug_report sh Figure 7 25 Bug...

Page 82: ...MSC SM2S IMX8MINI 82 87 User Manual Select Edit User Message Figure 7 26 Bug report User message editor Enter bug report message and press Ctrl O and Ctrl X ...

Page 83: ...y you can then view the message with the board report hardware information Figure 7 27 Bug report Viewer page Press Create a zip file and select the components you want to send e g bootlog mscio ini last kernel logs dmesg or the installed hardware ...

Page 84: ...g report Zip archive content selector Press Save ZIP to a disc and select the filesystem where to store the zip file It is recommended to use a USB stick Send the files msc_bug_report_brief txt and msc_bug_report zip to MSC support msc technologies eu ...

Page 85: ... Hot fixes are tagged with a newer date stamp e g LC984_20160113_V0_4_0 A hot fix can be checked out explicitly using these tags When MSC LDK is checked out the first time all hot fixes are applied automatically To update an older checkout and to pull all the newer hot fixes run scripts update py from the MSC LDK root directory This will update MSC LDK and all layers Depending on the kind of hot f...

Page 86: ...branch Here update py must also be used However on the SM2S IMX8MINI currently the master branch is not applicable instead all current changes are applied as hotfixes to the MSC LDK release state of v1 5 0 State March 2021 This may change soon as MSC is working on the next release already Please ask Avnet Integrated MSC Technical Support for respective last state at any given time ...

Page 87: ... 14N0261I variant Both CAN transceivers drive SPI 0 1 _DIN signals low even though not selected by chip select signal Source Hardware Workaround Not specified yet 8 2 Support For additional help please contact Avnet Integrated MSC Technical Support Phone 49 8165 906 200 WWW https www msc technologies eu support boards html Email support boards avnet eu ...

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