51
POST (hex)
Description
24h ~ 26h Reserved
27h
Initialize INT 09 buffer
28h
Reserved
29h
1. Program CPU internal MTRR (P6 & PII) for 0-640K memory address.
2. Initialize the APIC for Pentium class CPU.
3. Program early chipset according to CMOS setup. Example: onboard IDE
controller.
4. Measure CPU speed.
5. Invoke video BIOS.
2Ah ~ 2Ch Reserved
2Dh
1. Initialize multi-language
2. Put information on screen display, including Award title, CPU type, CPU
speed ….
2Eh ~ 32h Reserved
33h
Reset keyboard except Winbond 977 series Super I/O chips.
34h ~ 3Bh Reserved
3Ch
Test 8254
3Dh
Reserved
3Eh
Test 8259 interrupt mask bits for channel 1.
3Fh
Reserved
40h
Test 8259 interrupt mask bits for channel 2.
41h ~ 42h Reserved
43h
Test 8259 functionality.
44h ~ 46h Reserved
47h
Initialize EISA slot
48h
Reserved
49h
1. Calculate total memory by testing the last double word of each 64K page.
2. Program write allocation for AMD K5 CPU.
4Ah ~ 4Dh Reserved
4Eh
1. Program MTRR of M1 CPU
2. Initialize L2 cache for P6 class CPU & program CPU with proper cacheable
range.
3. Initialize the APIC for P6 class CPU.
4. On MP platform, adjust the cacheable range to smaller one in case the
cacheable ranges between each CPU are not identical.
4Fh
Reserved
50h
Initialize USB