Atmel XMEGA B, User Manual

Page: 280 / 415

280 XMEGA B [DATASHEET]
8291B–AVR–01/2013

Bit 4 – FERR: Frame Error
The FERR flag indicates the state of the first stop bit of the next readable frame stored in the receive buffer. The bit is set
if the received character had a frame error, i.e., the first stop bit was zero, and cleared when the stop bit of the received
data is one. This bit is valid until the receive buffer (DATA) is read. FERR is not affected by setting the number of stop
bits used, as it always uses only the first stop bit. Always write this bit location to zero when writing the STATUS register.
This flag is not used in master SPI mode operation.

Bit 3 – BUFOVF: Buffer Overflow
This flag indicates data loss due to a receiver buffer full condition. This flag is set if a buffer overflow condition is
detected. A buffer overflow occurs when the receive buffer is full (two characters) with a new character waiting in the
receive shift register and a new start bit is detected. This flag is valid until the receive buffer (DATA) is read. Always write
this bit location to zero when writing the STATUS register.
This flag is not used in master SPI mode operation.

Bit 2 – PERR: Parity Error
If parity checking is enabled and the next character in the receive buffer has a parity error, this flag is set. If parity check
is not enabled, this flag will always be read as zero. This bit is valid until the receive buffer (DATA) is read. Always write
this bit location to zero when writing the STATUS register. For details on parity calculation, refer to
“Parity Bit Calculation”
on page 269 .
This flag is not used in master SPI mode operation.

Bit 1 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this
register is written.
 Bit 0 – RXB8: Receive Bit 8
RXB8 is the ninth data bit of the received character when operating with serial frames with nine data bits. When used,
this bit must be read before reading the low bits from DATA.
This bit is unused in master SPI mode operation.
21.15.3 CTRLA – Control register A

Bit 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.

Bit 5:4 – RXCINTLVL[1:0]: Receive Complete Interrupt Level
These bits enable the receive complete interrupt and select the interrupt level, as described in “Interrupts and
Programmable Multilevel Interrupt Controller” on page 118 . The enabled interrupt will be triggered when the RXCIF flag
in the STATUS register is set.

Bit 3:2 – TXCINTLVL[1:0]: Transmit Complete Interrupt Level
These bits enable the transmit complete interrupt and select the interrupt level, as described in “Interrupts and
Programmable Multilevel Interrupt Controller” on page 118 . The enabled interrupt will be triggered when the TXCIF flag
in the STATUS register is set.

Bit 1:0 – DREINTLVL[1:0]: Data Register Empty Interrupt Level
These bits enable the data register empty interrupt and select the interrupt level, as described in “Interrupts and
Programmable Multilevel Interrupt Controller” on page 118 . The enabled interrupt will be triggered when the DREIF flag
in the STATUS register is set.
Bit 7 6 5 4 3 2 1 0
+0x03
– – RXCINTLVL[1:0] TXCINTLVL[1:0] DREINTLVL[1:0]
Read/Write R R R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0