Atmel XMEGA B, User Manual

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229 XMEGA B [DATASHEET]
8291B–AVR–01/2013

Bit 1 – BUSNACK0: Data Buffer 0 Not Acknowledge Flag
When this flag is set, the USB module will discard incoming data to data buffer 0 in an OUT transaction, and will not
return any data from data buffer 0 in an IN transaction. For control, bulk, and interrupt endpoints, a NAK handshake is
returned. This flag is cleared by writing a one to its bit location.

Bit 0 – TOGGLE: Data Toggle Flag
This indicates if a DATA0 or DATA1 PID is expected in the next data packet for an output endpoint, and if a DATA0 or
DATA1 PID will be sent in the next transaction for an input endpoint. This bit has no effect for isochronous endpoints,
where both DATA0 and DATA1 PIDs are accepted for output endpoint, and only DATA0 PIDs are sent for input
endpoints.
18.14.2 CTRL – Control
Note: 1. For isochronous endpoints.

Bit 7:6 – TYPE[1:0]: Endpoint Type
These bits are used to enable and select the endpoint type. If the endpoint is disabled, the remaining seven endpoint
configuration bytes are never read or written by the USB module, and their SRAM locations are free to use for other
application data.
Table 18-4. Endpoint type.
 Bit 5 – MULTIPKT: Multipacket Transfer Enable
Setting this bit enables multipacket transfers. Multipacket transfer enables a data payload exceeding the maximum
packet size of an endpoint to be transferred as multiple packets without interrupts or software intervention. See
“Multipacket Transfers” on page 216 for details on multipacket transfers.
 Bit 4 – PINGPONG: Ping-pong Enable
Setting this bit enables ping-pong operation. Ping-pong operation enables both endpoints (IN and OUT) with same
address to be used in the same direction to allow double buffering and maximize throughput. The endpoint in the
opposite direction must be disabled when ping-pong operation is enabled. Ping-pong operation is not possible for control
endpoints. See
“Ping-pong Operation” on page 215 for details.

Bit 3 – INTDSBL: Interrupt Disable
Setting this bit disables all enabled interrupts from the endpoint. Hence, only the interrupt flags in the STATUS register
are updated when interrupt conditions occur. The FIFO does not store this endpoint configuration table address upon
transaction complete for the endpoint when interrupts are disabled for an endpoint. Clearing this bit enables all previously
enables interrupts again.
Bit 7 6 5 4 3 2 1 0
+0x01
TYPE[1:0] MULTIPKT PINGPONG INTDSBL
STALL SIZE[1:0]
SIZE[2:0]
(1)
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
TYPE[1:0] Group Configuration Description
00 DISABLE Endpoint enabled
01 CONTROL Control
10 BULK Bulk/interrupt
11 ISOCHRONOUS Isochronous