Atmel SAM9X25, Manual

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9. ARM926EJ-S
™
9.1 Description
The ARM926EJ-S processor is a member of the ARM9
™
family of general-purpose microproces-
sors. The ARM926EJ-S implements ARM architecture version 5TEJ and is targeted at multi-
tasking applications where full memory management, high performance, low die size and low
power are all important features.
The ARM926EJ-S processor supports the 32-bit ARM and 16-bit THUMB instruction sets,
enabling the user to trade off between high performance and high code density. It also supports
8-bit Java instruction set and includes features for efficient execution of Java bytecode, provid-
ing a Java performance similar to a JIT (Just-In-Time compilers), for the next generation of Java-
powered wireless and embedded devices. It includes an enhanced multiplier design for
improved DSP performance.
The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist
in both hardware and software debug.
The ARM926EJ-S provides a complete high performance processor subsystem, including:
• an ARM9EJ-S
™
integer core
• a Memory Management Unit (MMU)
• separate instruction and data AMBA AHB bus interfaces
9.2 Embedded Characteristics
• ARM9EJ-S
™
Based on ARM
®
Architecture v5TEJ with Jazelle Technology
• Three Instruction Sets
– ARM
®
High-performance 32-bit Instruction Set
– Thumb
®
High Code Density 16-bit Instruction Set
– Jazelle
®
8-bit Instruction Set
• 5-Stage Pipeline Architecture when Jazelle is not Used
– Fetch (F)
– Decode (D)
– Execute (E)
– Memory (M)
– Writeback (W)
• 6-Stage Pipeline when Jazelle is Used
– Fetch
– Jazelle/Decode (Two Cycles)
– Execute
– Memory
– Writeback
• ICache and DCache
– Virtually-addressed 4-way Set Associative Caches
– 8 Words per Line
– Critical-word First Cache Refilling